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    Bit line precharge circuit
    1.
    发明授权
    Bit line precharge circuit 失效
    位线预充电电路

    公开(公告)号：US5754487A

    公开(公告)日：1998-05-19

    申请号：US749277

    申请日：1996-11-13

    申请人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

    发明人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/12

    摘要： An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.

    摘要翻译： 包括多个位线对的SRAM，连接在每对位线之间的存储单元，以及用于检测外部施加的地址信号的转换以产生检测脉冲信号的地址转换检测电路， 改进的位线预充电电路每位线对只需要两个晶体管。 新的预充电电路由位线预充电控制信号发生器控制，用于产生由源电压和接地电压之间连接的阻抗比确定的控制信号。

    Data output circuits having enhanced ESD resistance and related methods
    3.
    发明授权
    Data output circuits having enhanced ESD resistance and related methods 失效
    数据输出电路具有增强的ESD电阻和相关方法

    公开(公告)号：US5994943A

    公开(公告)日：1999-11-30

    申请号：US963792

    申请日：1997-11-04

    申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

    发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

    IPC分类号： G11C11/417 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03H5/00 ,  H02H3/20

    CPC分类号： H01L27/0266

    摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

    摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

    Data output circuits having enhanced ESD resistance and related methods
    5.
    发明授权
    Data output circuits having enhanced ESD resistance and related methods 有权
    数据输出电路具有增强的ESD电阻和相关方法

    公开(公告)号：US06271705B1

    公开(公告)日：2001-08-07

    申请号：US09448534

    申请日：1999-11-22

    申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

    发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

    IPC分类号： H03K500

    CPC分类号： H01L27/0266

    摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

    摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

    Integrated circuit memory devices having hierarchical bit line selection circuits therein
    7.
    发明申请
    Integrated circuit memory devices having hierarchical bit line selection circuits therein 失效
    具有分层位线选择电路的集成电路存储器件

    公开(公告)号：US20060062061A1

    公开(公告)日：2006-03-23

    申请号：US11041675

    申请日：2005-01-24

    申请人： Young-Ho Suh ,  Hyun-Geun Byun

    发明人： Young-Ho Suh ,  Hyun-Geun Byun

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/0688 ,  H01L27/1108

    摘要： Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

    摘要翻译： 集成电路存储器件包括电耦合到第一对位线的第一列存储器单元和位线预充电和选择电路。 该位线预充电和选择电路包括薄膜晶体管的至少一个堆叠布置。 这些薄膜晶体管包括第一PMOS薄膜上拉晶体管和第一NMOS薄膜通过晶体管。 这些薄膜晶体管电耦合到第一对位线之一。 存储单元的第一列包括一列TFT SRAM单元。

    Integrated circuit memory devices including overlapping power lines and bit lines
    8.
    发明授权
    Integrated circuit memory devices including overlapping power lines and bit lines 失效
    集成电路存储器件包括重叠的电源线和位线

    公开(公告)号：US5936875A

    公开(公告)日：1999-08-10

    申请号：US979573

    申请日：1997-11-26

    申请人： Dae-Yong Kim ,  Du-Eung Kim ,  Young-Ho Suh ,  Choung-Keun Kwak

    发明人： Dae-Yong Kim ,  Du-Eung Kim ,  Young-Ho Suh ,  Choung-Keun Kwak

    IPC分类号： G11C11/41 ,  G11C5/06 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C5/02

    CPC分类号： G11C5/063

    摘要： Integrated circuit memory devices include overlapping bit lines and power supply lines. The integrated circuit memory devices include a memory cell array in an integrated circuit substrate and a plurality of spaced apart bit lines on the memory cell array, extending in a first direction. A plurality of spaced apart power lines are also included on the memory cell array, extending in the first direction, and on at least one of the plurality of bit lines. The overlapping bit lines and power supply lines are insulated from one another, for example by providing these lines in first and second patterned conductive layers. Accordingly, higher density integrated circuit devices may be provided while allowing high speed operation and effective power supply voltage distribution.

    摘要翻译： 集成电路存储器件包括重叠位线和电源线。 集成电路存储器件包括在集成电路衬底中的存储单元阵列和在第一方向上延伸的存储单元阵列上的多个间隔开的位线。 多个间隔开的电源线还包括在存储单元阵列中，沿第一方向延伸，并且在多个位线中的至少一个位线上。 重叠的位线和电源线彼此绝缘，例如通过在第一和第二图案化导电层中提供这些线。 因此，可以提供更高密度的集成电路器件，同时允许高速操作和有效的电源电压分配。

    ROBOT SYSTEM BASED ON NETWORK AND EXECUTION METHOD OF THAT SYSTEM
    9.
    发明申请
    ROBOT SYSTEM BASED ON NETWORK AND EXECUTION METHOD OF THAT SYSTEM 审中-公开
    基于网络的机器人系统及其系统的执行方法

    公开(公告)号：US20090018698A1

    公开(公告)日：2009-01-15

    申请号：US11720397

    申请日：2005-04-27

    申请人： Hyun Kim ,  Kang-Woo Lee ,  Joo-Haeng Lee ,  Tae-Gun Kang ,  Ae-Kyeung Moon ,  Young-Ho Suh ,  Joon-Myun Cho ,  Young-Jo Cho

    发明人： Hyun Kim ,  Kang-Woo Lee ,  Joo-Haeng Lee ,  Tae-Gun Kang ,  Ae-Kyeung Moon ,  Young-Ho Suh ,  Joon-Myun Cho ,  Young-Jo Cho

    IPC分类号： G06F19/00

    CPC分类号： G05D1/0011

    摘要： The present invention relates to a network-based robot system and an executing method thereof. According to an exemplary embodiment of the present invention, predefine environment information is expressed in a universal data model (UDM) described by a linkage that shows a relationship among nodes, each node being an object of a virtual space abstracted by a real physical space. The universal data model is updated based on the context information, event occurrence information is transmitted to a task engine when the context information data value is changed, and the task engine executes a corresponding task through reasoning and invokes an external service. The robot can better recognize the context information by utilizing the external sensing function and external processing function. In addition, the robot system can provide an active service by reasoning the recognized context information and obtaining high-level information.

    摘要翻译： 本发明涉及基于网络的机器人系统及其执行方法。 根据本发明的示例性实施例，预定义环境信息在由链接描述的通用数据模型（UDM）中表示，所述链接显示节点之间的关系，每个节点是由真实物理空间抽象的虚拟空间的对象。 基于上下文信息来更新通用数据模型，当上下文信息数据值改变时事件发生信息被发送到任务引擎，并且任务引擎通过推理执行对应的任务并调用外部服务。 机器人可以通过利用外部感应功能和外部处理功能，更好地识别上下文信息。 此外，机器人系统可以通过推断识别的上下文信息并获得高级信息来提供主动服务。

    SRAM device capable of performing burst operation
    10.
    发明授权
    SRAM device capable of performing burst operation 有权
    能够执行突发操作的SRAM器件

    公开(公告)号：US07304908B2

    公开(公告)日：2007-12-04

    申请号：US11333650

    申请日：2006-01-17

    申请人： Young-Ho Suh

    发明人： Young-Ho Suh

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C2207/2245

    摘要： Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.

    摘要翻译： 提供存储器件，其能够响应于单个字线的选择而同时向存储器写入/读取多个数据位，并且能够控制数据输入/输出用于中断突发操作，从而执行突发操作 中断而不必使用复杂的控制电路。