公开(公告)号：US11030378B1

公开(公告)日：2021-06-08

申请号：US16904534

申请日：2020-06-17

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/3947 ,  G06F30/392

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

公开(公告)号：US10963617B1

公开(公告)日：2021-03-30

申请号：US16735658

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  William Robert Reece ,  Natarajan Viswanathan ,  Mehmet Can Yildiz ,  Gracieli Posser ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F30/394

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

公开(公告)号：US10936777B1

公开(公告)日：2021-03-02

申请号：US16777661

申请日：2020-01-30

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/337 ,  G06F30/392 ,  G06F30/31 ,  G06F30/396 ,  G06F30/3312

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

公开(公告)号：US10796049B1

公开(公告)日：2020-10-06

申请号：US16228481

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Kwangsoo Han ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50 ,  G06F30/3312 ,  G06F30/337 ,  G06F111/10 ,  G06F119/12 ,  G06F30/30

Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

公开(公告)号：US10755024B1

公开(公告)日：2020-08-25

申请号：US16148182

申请日：2018-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Wing Kai Chow ,  Mehmet Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/327 ,  G06F111/20 ,  G06F111/04

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

公开(公告)号：US10509878B1

公开(公告)日：2019-12-17

申请号：US15688730

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Wen-Hao Liu

IPC: G06F17/50 ,  G06F1/10

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

公开(公告)号：US10460066B1

公开(公告)日：2019-10-29

申请号：US15649443

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

公开(公告)号：US10380287B1

公开(公告)日：2019-08-13

申请号：US15638048

申请日：2017-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

公开(公告)号：US10318693B1

公开(公告)日：2019-06-11

申请号：US15690043

申请日：2017-08-29

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Zhuo Li ,  Charles Jay Alpert ,  William Robert Reece ,  Thomas Andrew Newton

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

公开(公告)号：US10102328B1

公开(公告)日：2018-10-16

申请号：US15060020

申请日：2016-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Jay Alpert ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.