公开(公告)号：US20090102535A1

公开(公告)日：2009-04-23

申请号：US11967036

申请日：2007-12-29

Applicant: CHUN-JEN CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： CHUN-JEN CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: G06F1/04

CPC classification number: G06F1/06 ,  G06F1/10

Abstract: A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2.

Abstract translation: 用于多个负载的时钟信号电路包括时钟发生器和M个负载。 时钟发生器包括输出具有相同频率的时钟信号的N个时钟发生器引脚。 N个时钟发生器引脚都连接到连接点。 连接点分别通过M个发送线路连接到M个负载，其中M大于N，M和N分别为大于2的整数。

公开(公告)号：US20070205846A1

公开(公告)日：2007-09-06

申请号：US11309480

申请日：2006-08-11

Applicant: CHUN-JEN CHEN ,  SHOU-KUO HSU

Inventor： CHUN-JEN CHEN ,  SHOU-KUO HSU

IPC: H04B3/04

CPC classification number: H02M1/126

Abstract: A filter circuit includes a signal source, an inductor, a load, and a compensator. The inductor and the load are connected between two terminals of the signal source in series. The compensator is connected in parallel with the inductor.

Abstract translation: 滤波器电路包括信号源，电感器，负载和补偿器。 电感和负载连接在信号源的两个端子之间。 补偿器与电感并联。

公开(公告)号：US20130204558A1

公开(公告)日：2013-08-08

申请号：US13596063

申请日：2012-08-28

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: G06F19/00 ,  G01R21/06

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method for calculating efficiency of a power supply system includes: displaying a parameter selection interface on the display unit for selecting power supply parameters and transmission line parameters. Obtaining power supply parameters and transmission line parameters selected by the user via the parameter selection interface when determining the user has finished the selection. Determining a efficiency of a selected power supply of the power supply parameters according to the relationship table, and calculating a sum efficiency according to the obtained power supply parameters and the transmission line parameters and the efficiency of the selected power supply. And calculating a total efficiency of the power supply system according to each sum efficiency when determining that all of the power supplies of the power supply system have been selected.

Abstract translation: 一种用于计算电源系统的效率的方法包括：在显示单元上显示参数选择界面，用于选择电源参数和传输线参数。 当确定用户已经完成选择时，通过参数选择界面获取用户选择的电源参数和传输线参数。 根据关系表确定电源参数的选定电源的效率，并根据获得的电源参数和传输线参数以及所选择的电源的效率来计算总和效率。 并且当确定已经选择了电源系统的所有电源时，根据每个总效率来计算电力供应系统的总效率。

公开(公告)号：US20130006561A1

公开(公告)日：2013-01-03

申请号：US13451433

申请日：2012-04-19

Applicant: PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  YING-TSO LAI ,  EN-SHUO CHANG

Inventor： PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  YING-TSO LAI ,  EN-SHUO CHANG

IPC: G06F19/00

CPC classification number: G06F17/5036 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/82

Abstract: In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification.

Abstract translation: 在使用计算设备分析印刷电路板（PCB）的信号组延迟的方法中，计算设备连接到从PCB的一对数据信号线和时钟信号线测量S参数的信号测量装置 。 该方法基于S参数分析数据信号线和时钟信号线的差分损耗系数，并根据差分损耗计算数据信号线的第一信号延迟和时钟信号线的第二信号延迟 系数。 该方法还根据第一信号延迟和第二信号延迟分析PCB的信号组延迟，并且如果信号组延迟不满足PCB设计规范，则在显示装置上显示信号组延迟。

公开(公告)号：US20120314391A1

公开(公告)日：2012-12-13

申请号：US13183452

申请日：2011-07-15

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: H05K7/12 ,  H05K7/00

CPC classification number: H05K1/0231 ,  H05K1/0222 ,  H05K2201/09618

Abstract: A circuit board includes a base board defining a number of via holes, a power supply connection unit, a load connection unit, and at least one capacitor connection unit(s). Each of the at least one capacitor connection unit(s) includes two capacitor connectors, and one of the two capacitor connectors is positioned nearer to the power supply connection unit and farther away from the load connection unit than the other. The via holes are divided into at least one group(s) corresponding to each of the capacitor connection unit(s), and all of the via holes in each of the group(s) are equidistantly positioned along a semicircle arc surrounding the capacitor connector of the capacitor connection unit corresponding to the group that is positioned nearer to the power supply connection unit.

Abstract translation: 电路板包括限定多个通孔的基板，电源连接单元，负载连接单元和至少一个电容器连接单元。 所述至少一个电容器连接单元中的每一个包括两个电容器连接器，并且所述两个电容器连接器中的一个位于更靠近所述电源连接单元的位置，并且远离所述负载连接单元。 通孔被分成与电容器连接单元中的每一个相对应的至少一个组，并且每个组中的所有通路孔沿着围绕电容器连接器的半圆弧等距定位 的电容器连接单元对应于位于更靠近电源连接单元的组的电容器连接单元。

公开(公告)号：US20120278784A1

公开(公告)日：2012-11-01

申请号：US13315291

申请日：2011-12-09

Applicant: DAN-CHEN WU ,  SHOU-KUO HSU ,  CHENG-HSIEN LEE ,  CHUN-JEN CHEN

Inventor： DAN-CHEN WU ,  SHOU-KUO HSU ,  CHENG-HSIEN LEE ,  CHUN-JEN CHEN

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device.

Abstract translation: 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择电力线。 该方法从PCB的布局图搜索与所选择的电力线重叠的一条或多条信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线和所选电力线的属性数据，并将所搜索的信号线和所选电力线的属性数据显示在电子设备的显示装置上。

公开(公告)号：US20120176110A1

公开(公告)日：2012-07-12

申请号：US13008037

申请日：2011-01-18

Applicant: DUEN-YI HO ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU ,  TSUNG-SHENG HUANG

Inventor： DUEN-YI HO ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU ,  TSUNG-SHENG HUANG

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M2001/0009

Abstract: A voltage regulating circuit includes a pulse width modulation controller, a current sense circuit, a voltage feedback circuit, and a gain-and-bias circuit. The current sense circuit includes an inductor and a capacitor. The voltage feedback circuit includes first and second resistors. The gain-and-bias circuit includes an operational amplifier. A first terminal of the capacitor is connected to an inverting input terminal of the operational amplifier through a third resistor. A second terminal of the capacitor is connected to a non-inverting input terminal of the operational amplifier through a fourth resistor. The inverting input terminal of the amplifier is connected to an output terminal of the operational amplifier through a fifth resistor. The non-inverting input terminal of the operational amplifier is grounded through a sixth resistor. The output terminal of the operational amplifier is connected to the node between the first and second resistors through a seventh resistor.

Abstract translation: 电压调节电路包括脉宽调制控制器，电流检测电路，电压反馈电路和增益与偏置电路。 电流检测电路包括电感器和电容器。 电压反馈电路包括第一和第二电阻器。 增益和偏置电路包括运算放大器。 电容器的第一端子通过第三电阻器连接到运算放大器的反相输入端子。 电容器的第二端子通过第四电阻器连接到运算放大器的非反相输入端子。 放大器的反相输入端通过第五个电阻连接到运算放大器的输出端。 运算放大器的非反相输入端通过第六个电阻接地。 运算放大器的输出端通过第七电阻连接到第一和第二电阻之间的节点。

公开(公告)号：US20110094787A1

公开(公告)日：2011-04-28

申请号：US12647431

申请日：2009-12-25

Applicant: YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

Inventor： YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K3/3447 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2203/0242 ,  Y10T29/49155

Abstract: A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole passes through the printed circuit board. A number of thermal engravings are defined in the layer around the through hole. Each thermal engraving is a groove defined in the surface of the layer, without covered with the layer of copper. The number of thermal engravings are not in contact with each other.

Abstract translation: 印刷电路板包括一层。 铜层被覆盖在该层的表面上。 通孔穿过印刷电路板。 在通孔周围的层中限定了许多热雕刻。 每个热雕刻是在层的表面中限定的凹槽，而不被铜层覆盖。 热雕刻的数量彼此不接触。

公开(公告)号：US20110047524A1

公开(公告)日：2011-02-24

申请号：US12701677

申请日：2010-02-08

Applicant: HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  CHUN-JEN CHEN ,  SHOU-KUO HSU ,  DUEN-YI HO ,  YUNG-CHIEH CHEN

Inventor： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  CHUN-JEN CHEN ,  SHOU-KUO HSU ,  DUEN-YI HO ,  YUNG-CHIEH CHEN

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A system and method for inspecting layout of a printed circuit board (PCB) provides a graphical user interface (GUI). The GUI displays a layout of the PCB. High side pins of a pulse width modulation (PWM) controller and a component connected to a high side pin are found. If the component is a metallic oxide semiconductor field effect transistor (MOSFET), the system calculate absolute a linear distance and a trace distance between a source pin of the MOSFET and a capacitor pin of a coupling capacitor connected to the source pin. If the linear distance, the trace distance and a capacitance of the coupling capacitor accord with a layout standard, the layout of the PCB is determined to be up to standard.

Abstract translation: 用于检查印刷电路板（PCB）的布局的系统和方法提供图形用户界面（GUI）。 GUI显示PCB的布局。 发现脉冲宽度调制（PWM）控制器的高端引脚和连接到高端引脚的元件。 如果组件是金属氧化物半导体场效应晶体管（MOSFET），则该系统计算绝缘线性距离和MOSFET的源极引脚与连接到源极引脚的耦合电容的电容引脚之间的走线距离。 如果线性距离，迹线距离和耦合电容的电容符合布局标准，则PCB的布局被确定为达到标准。

公开(公告)号：US20110012426A1

公开(公告)日：2011-01-20

申请号：US12551463

申请日：2009-08-31

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO

IPC: H02J1/00 ,  G06F17/50

CPC classification number: G06F1/26 ,  G06F17/50 ,  H02J1/00 ,  Y10T307/25 ,  Y10T307/555

Abstract: A power supply system includes a power supply, a daughterboard, and a motherboard. Output currents of power connectors of the motherboard and impedances of copper foils between every two adjacent power connectors of the motherboard are obtained via simulation. A voltage of one power connector of the motherboard is predetermined. Therefore, desired impedances of copper foils between VRM connectors and corresponding power connectors on the daughter board are determined via calculations, to make currents passing through the power connectors of the motherboard equal to each other.

Abstract translation: 电源系统包括电源，子板和主板。 母板电源连接器的输出电流和母板每两个相邻电源连接器之间铜箔的阻抗通过仿真获得。 母板的一个电源连接器的电压是预先确定的。 因此，通过计算确定VRM连接器与子板上相应的电源连接器之间的铜箔的期望阻抗，以使通过主板的电源连接器的电流彼此相等。