公开(公告)号：US07534643B2

公开(公告)日：2009-05-19

申请号：US11448496

申请日：2006-06-07

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L29/66659

Abstract: A method for fabricating a CMOS image sensor includes: forming a gate electrode on a pixel region of the semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region; forming a first lightly doped n-type diffusion region on the photodiode region; forming a second lightly doped n-type diffusion region on the transistor region; consecutively forming first and second insulating layers on the entire surface of the semiconductor substrate; removing a predetermined portion of the second insulation layer on the transistor region and the middle resistor region; forming a third insulation layer on the entire surface of the semiconductor substrate; forming sidewalls of the first insulating layer and the third insulating layer on the gate electrode and the polysilicon pattern by performing an etch-back process; and heavily doping n-type impurities in the transistor region and the polysilicon pattern.

Abstract translation: 一种制造CMOS图像传感器的方法，包括：在半导体衬底的像素区域上形成栅极电极，同时在中间电阻器区域上形成多晶硅图案; 在所述光电二极管区域上形成第一轻掺杂n型扩散区; 在所述晶体管区上形成第二轻掺杂n型扩散区; 在半导体衬底的整个表面上连续形成第一和第二绝缘层; 去除晶体管区域和中间电阻器区域上的第二绝缘层的预定部分; 在所述半导体衬底的整个表面上形成第三绝缘层; 通过执行回蚀工艺在栅电极和多晶硅图案上形成第一绝缘层和第三绝缘层的侧壁; 并在晶体管区域和多晶硅图案中重掺杂n型杂质。

公开(公告)号：US07507626B2

公开(公告)日：2009-03-24

申请号：US11647021

申请日：2006-12-27

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.

Abstract translation: 公开了一种闪存器件的浮动栅极，其中在半导体衬底上形成隧道氧化物层，并且浮栅形成为具有凸顶表面的透镜的形状。

公开(公告)号：US07494863B2

公开(公告)日：2009-02-24

申请号：US11485361

申请日：2006-07-13

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/8234 ,  H01L21/8244

CPC classification number: H01L28/40 ,  H01L21/3212 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632

Abstract: Disclosed is a method for manufacturing a capacitor in a semiconductor device. A method consistent with the present invention includes forming a lower electrode on a semiconductor substrate; forming a first interlevel dielectric layer on an entire surface of the semiconductor substrate, covering the lower electrode; selectively removing the first interlevel dielectric layer to form an opening exposing a surface of the lower electrode; sequentially forming a dielectric layer and a conductive layer over the entire surface of the semiconductor substrate including the opening; planarizing the conductive layer to form an upper electrode in the opening; and forming a second interlevel dielectric layer over the entire surface of the semiconductor substrate including the upper electrode.

Abstract translation: 公开了一种在半导体器件中制造电容器的方法。 符合本发明的方法包括在半导体衬底上形成下电极; 在所述半导体衬底的整个表面上形成第一层间电介质层，覆盖所述下电极; 选择性地去除所述第一层间电介质层以形成暴露所述下电极的表面的开口; 在包括该开口的半导体衬底的整个表面上依次形成介电层和导电层; 平面化导电层以在开口中形成上电极; 以及在包括上电极的半导体衬底的整个表面上形成第二层间电介质层。

公开(公告)号：US20080156970A1

公开(公告)日：2008-07-03

申请号：US12001652

申请日：2007-12-11

Applicant: Chang Hun Han ,  Hea Soo Chung

Inventor： Chang Hun Han ,  Hea Soo Chung

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14643 ,  H01L27/14685

Abstract: The present invention provides an image sensor, and methods of manufacturing the same, that includes a color filter layer on a semiconductor substrate, and a microlens array on the color filter layer, in which the microlens includes a transparent conductive layer.

Abstract translation: 本发明提供了一种图像传感器及其制造方法，其包括半导体衬底上的滤色器层和滤色器层上的微透镜阵列，其中微透镜包括透明导电层。

公开(公告)号：US07217967B2

公开(公告)日：2007-05-15

申请号：US10746980

申请日：2003-12-23

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L27/148

CPC classification number: H01L27/14609 ,  H01L27/14603 ,  H01L27/1463

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

公开(公告)号：US07101759B2

公开(公告)日：2006-09-05

申请号：US10750252

申请日：2003-12-31

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/115

Abstract: Methods of fabricating nonvolatile memory devices are disclosed. A disclosed method comprises forming a trench isolation layer on a substrate; forming an oxide layer and a polysilicon layer; forming a sacrificial layer on the polysilicon layer; forming a photoresist pattern on the sacrificial layer; performing an etching process using the photoresist pattern as a mask and, at the same time, attaching polymers on sidewalls of the etched sacrificial layer to form polymer layers, the polymers being generated from the etching of the sacrificial layer; and forming a floating gate and a tunnel oxide by removing part of the polysilicon layer and the oxide layer using the polymer layers and the photoresist pattern as a mask. The disclosed method can increase the width of a floating gate by using polymer layers in fabricating a two-bit type cell, thereby ensuring a higher coupling ratio compared to the coupling ratio of a conventional two-bit type cell.

Abstract translation: 公开了制造非易失性存储器件的方法。 所公开的方法包括在衬底上形成沟槽隔离层; 形成氧化物层和多晶硅层; 在所述多晶硅层上形成牺牲层; 在牺牲层上形成光致抗蚀剂图案; 执行使用光致抗蚀剂图案作为掩模的蚀刻工艺，并且同时将聚合物附着在蚀刻的牺牲层的侧壁上以形成聚合物层，该聚合物是从牺牲层的蚀刻产生的; 并且通过使用聚合物层和光致抗蚀剂图案作为掩模，通过去除多晶硅层和氧化物层的一部分来形成浮置栅极和隧道氧化物。 所公开的方法可以通过在制造两位型电池中使用聚合物层来增加浮动栅极的宽度，由此确保与传统的两位型电池的耦合比相比更高的耦合比。

公开(公告)号：US20060138484A1

公开(公告)日：2006-06-29

申请号：US11319067

申请日：2005-12-28

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L31/113 ,  H01L31/00 ,  H01L27/10

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

Abstract: A CMOS image sensor includes a first conductive type semiconductor substrate having an active region and a device isolation region, a device isolation film formed in the device isolation region of the semiconductor substrate, a second conductive type diffusion region formed in the active region of the semiconductor substrate, and an ion implantation prevention layer formed in the vicinity of the device isolation film, including a boundary portion between the device isolation film and the second conductive type diffusion region.

Abstract translation: CMOS图像传感器包括具有有源区和器件隔离区的第一导电类型半导体衬底，形成在半导体衬底的器件隔离区中的器件隔离膜，形成在半导体的有源区中的第二导电型扩散区 衬底和形成在器件隔离膜附近的离子注入防止层，包括器件隔离膜和第二导电类型扩散区之间的边界部分。

公开(公告)号：US06984590B2

公开(公告)日：2006-01-10

申请号：US10743483

申请日：2003-12-22

Applicant: Chang Hun Han ,  Dong Oog Kim

Inventor： Chang Hun Han ,  Dong Oog Kim

IPC: H01L21/20 ,  H01L21/265

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L21/324

Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Abstract translation: 公开了一种制造EEPROM器件的方法。 示例性方法在半导体衬底上形成屏幕氧化膜，在屏幕氧化膜上形成限定栅极绝缘膜形成区域的第一离子注入掩模，并在半导体衬底和第一离子注入掩模上执行第一离子注入。 该示例方法还执行半导体衬底的第一退火，去除屏蔽氧化物膜和第一离子注入掩模，并在半导体衬底上形成栅极氧化膜。 此外，该示例性方法形成在栅极氧化膜上限定栅极绝缘膜形成区域的第二离子注入掩模，在半导体衬底和第二离子注入掩模上执行第二离子注入，对半导体衬底进行第二退火， 去除第二离子注入掩模; 并在栅极氧化膜上形成隧道氧化膜。

公开(公告)号：US06902979B2

公开(公告)日：2005-06-07

申请号：US10201860

申请日：2002-07-24

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/76 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L27/11253 ,  H01L27/105 ,  H01L27/11293

Abstract: A method for manufacturing a mask ROM of flat cell structure. The method includes the steps of: providing a semiconductor substrate having a flat cell array region and a peripheral circuit region; forming a first and a second mask patterns exposing a substrate portions corresponding to a diffusion layer formation region of the flat cell array region and a device isolation layer of the peripheral circuit region; ion-implanting an impurity in the exposed substrate portions; forming a trench by etching the exposed substrate portion peripheral circuit region; forming a linear oxide layer on the first and the second mask patterns and the surface of the trench, a diffusion layer on the flat cell array region, and a barrier oxide layer on the surface of diffusion layer in accordance with a thermal oxidation process; depositing an oxide layer on the linear oxide layer to fill up the trench; polishing the oxide layer to expose the surface of the first and the second mask patterns; and forming a diffusion layer on the flat cell array region and a trench type isolation layer on the peripheral circuit region by removing the first and the second mask patterns.

Abstract translation: 一种扁平单元结构的掩模ROM的制造方法。 该方法包括以下步骤：提供具有扁平单元阵列区域和外围电路区域的半导体衬底; 形成暴露与所述扁平单元阵列区域的扩散层形成区域对应的衬底部分和所述外围电路区域的器件隔离层的第一和第二掩模图案; 在暴露的衬底部分中离子注入杂质; 通过蚀刻暴露的基板部分外围电路区域形成沟槽; 在第一和第二掩模图案和沟槽的表面上形成线性氧化物层，在平坦单元阵列区域上形成扩散层，根据热氧化工艺在扩散层的表面上形成阻挡氧化物层; 在所述线性氧化物层上沉积氧化物层以填充所述沟槽; 抛光所述氧化物层以暴露所述第一和第二掩模图案的表面; 以及通过去除第一和第二掩模图案，在平坦单元阵列区域上形成扩散层和外围电路区域上的沟槽型隔离层。

公开(公告)号：US20130135786A1

公开(公告)日：2013-05-30

申请号：US13520031

申请日：2011-05-27

Applicant: Chang Wook Kim ,  Dong Chan Park ,  Ju Young Song ,  Sang Hun Lee ,  Sung Bae Cho ,  Hyun Ho Yang ,  Jun Bo Yoon ,  Dong Hun Choi ,  Chang Hun Han

Inventor： Chang Wook Kim ,  Dong Chan Park ,  Ju Young Song ,  Sang Hun Lee ,  Sung Bae Cho ,  Hyun Ho Yang ,  Jun Bo Yoon ,  Dong Hun Choi ,  Chang Hun Han

IPC: H01G5/04

CPC classification number: H01G5/04 ,  H01G5/18

Abstract: Disclosed herein is a variable capacitor and its driving method, the variable capacitor including, a movable first electrode; and a second electrode formed with an insulating film, fixed in place, and its insulating film contacting the first electrode that is moved.

Abstract translation: 这里公开了可变电容器及其驱动方法，所述可变电容器包括可移动的第一电极; 以及形成有绝缘膜的第二电极，固定在适当位置，其绝缘膜与被移动的第一电极接触。