公开(公告)号：US08296749B2

公开(公告)日：2012-10-23

申请号：US11966453

申请日：2007-12-28

申请人： Chengyan Zhao ,  Cheng Wang ,  Youfeng Wu

发明人： Chengyan Zhao ,  Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/45

CPC分类号： G06F9/45516

摘要： Disclosed are methods, machine readable medium and systems that dynamically translate binary programs. The dynamic binary translation may include identifying a hot code trace of a program. The translation may further include determining a completion ratio for the hot code trace. The translation may also include packaging the hot code trace into a transactional memory region in response to the completion ratio having a predetermined relationship to a threshold ratio.

摘要翻译： 公开了动态地翻译二进制程序的方法，机器可读介质和系统。 动态二进制翻译可以包括识别程序的热代码跟踪。 该翻译还可以包括确定热代码跟踪的完成率。 翻译还可以包括响应于具有与阈值比率的预定关系的完成比率将热代码跟踪封装到事务存储区域中。

公开(公告)号：US20120185714A1

公开(公告)日：2012-07-19

申请号：US13327683

申请日：2011-12-15

申请人： Jaewoong Chung ,  Youfeng Wu ,  Cheng Wang ,  Hanjun Kim

发明人： Jaewoong Chung ,  Youfeng Wu ,  Cheng Wang ,  Hanjun Kim

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F9/312 ,  G06F15/76 ,  G06F9/30

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/381 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

摘要： An apparatus, method and system is described herein for enabling intelligent recirculation of hot code sections. A hot code section is determined and marked with a begin and end instruction. When the begin instruction is decoded, recirculation logic in a back-end of a processor enters a detection mode and loads decoded loop instructions. When the end instruction is decoded, the recirculation logic enters a recirculation mode. And during the recirculation mode, the loop instructions are dispatched directly from the recirculation logic to execution stages for execution. Since the loop is being directly serviced out of the back-end, the front-end may be powered down into a standby state to save power and increase energy efficiency. Upon finishing the loop, the front-end is powered back on and continues normal operation, which potentially includes propagating next instructions after the loop that were prefetched before the front-end entered the standby mode.

摘要翻译： 本文描述了一种用于实现热代码部分的智能再循环的装置，方法和系统。 确定热代码部分并用开始和结束指令标记。 当开始指令被解码时，处理器后端的再循环逻辑进入检测模式并加载解码的循环指令。 当结束指令被解码时，再循环逻辑进入循环模式。 并且在再循环模式期间，循环指令直接从再循环逻辑调度到执行阶段以便执行。 由于循环是从后端直接服务的，所以前端可以掉电到待机状态，以节省电力并提高能源效率。 在完成循环后，前端被重新接通并继续正常操作，这可能包括在前端进入待机模式之前预取的循环之后传播下一个指令。

公开(公告)号：US08132158B2

公开(公告)日：2012-03-06

申请号：US11648005

申请日：2006-12-28

申请人： Cheng Wang ,  Youfeng Wu ,  Bratin Saha ,  Ali-Reza Adl-Tabatabai

发明人： Cheng Wang ,  Youfeng Wu ,  Bratin Saha ,  Ali-Reza Adl-Tabatabai

IPC分类号： G06F9/44

CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/466

摘要： A method and apparatus for ensuring integrity of transaction exit functions is herein described. Dead local data in a transaction is prevented from overwriting local variables associated with a transaction exit function. In a write-buffering Software Transactional Memory (STM) system, a commit function is associated with a private stack to store local variables to ensure write-back of local dead data in a write-buffer does not corrupt the commit function. Similarly, in a roll-back STM, an abort function is associated with a private stack to store local variables to ensure the roll-back of a program stack with local dead data from a write log does not corrupt the abort function. Alternatively, one stack may be used for the transaction including a first function and an exit function. Here, local dead variables are detected and prevented from overwriting local variables of the exit function.

摘要翻译： 这里描述了用于确保交易退出功能的完整性的方法和装置。 防止事务中的死地方数据覆盖与事务退出功能相关联的局部变量。 在写缓冲软件事务内存（STM）系统中，提交函数与专用堆栈相关联，以存储局部变量，以确保写缓冲区中的本地死数据的写回不会损坏提交函数。 类似地，在回滚STM中，中止功能与专用堆栈相关联以存储局部变量，以确保来自写入日志的本地死亡数据的程序堆栈的回滚不会破坏中止功能。 或者，可以将一个堆栈用于包括第一功能和退出功能的交易。 这里，检测并防止局部死变量覆盖退出函数的局部变量。

公开(公告)号：US07865885B2

公开(公告)日：2011-01-04

申请号：US11528801

申请日：2006-09-27

申请人： Youfeng Wu ,  Cheng Wang ,  Ho-seop Kim

发明人： Youfeng Wu ,  Cheng Wang ,  Ho-seop Kim

IPC分类号： G06F9/45

CPC分类号： G06F9/466

摘要： Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

摘要翻译： 通过选择应用代码的一部分作为可能的事务来执行应用代码的动态优化。 事务有一个属性，当它被执行时，它被原子地提交或原子地中止。 确定是否将应用程序代码的所选部分转换为事务包括确定是否将应用程序代码的一部分中的至少一个代码优化组合应用。 如果确定将优化组的代码优化中的至少一个应用于应用代码的部分，则优化被应用于代码的该部分，并将该部分代码转换为事务。

公开(公告)号：US20090313616A1

公开(公告)日：2009-12-17

申请号：US12139647

申请日：2008-06-16

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： A method and apparatus for improving parallelism through optimal code replication is herein described. An optimal replication factor for code is determined based on costs associated with a plurality of replication factors. The code is replicated by the optimal replication factor, and then the code is potentially executed in parallel to obtain parallelized efficient execution.

摘要翻译： 这里描述了通过最佳代码复制来改进并行性的方法和装置。 基于与多个复制因子相关联的成本来确定代码的最佳复制因子。 该代码由最佳复制因子复制，然后并行执行代码以获得并行化的高效执行。

公开(公告)号：US20080282257A1

公开(公告)日：2008-11-13

申请号：US11745403

申请日：2007-05-07

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/46

CPC分类号： G06F11/1497 ,  G06F8/457

摘要： Disclosed is a method for running a first code generated by a Software-based Redundant Multi-Threading (SRMT) compiler along with a second code generated by a normal compiler at runtime, the first code including a first function and a second function, the second code including a third function. The method comprises running the first function in a leading thread and a tailing thread (104); running the third function in a single thread (106), the leading thread calls the third function and running the second function in the leading thread and the tailing thread (108), the third function calls the second function. The present disclosure provides a mechanism for handling function calls wherein SRMT functions and binary functions can call each other irrespective of whether the callee function is a SRMT function or a binary function and thereby dynamically adjusts reliability and performance tradeoff based on run-time information and user selectable policies.

摘要翻译： 公开了一种用于在运行时运行由基于软件的冗余多线程（SRMT）编译器生成的第一代码以及由正常编译器生成的第二代码的方法，所述第一代码包括第一功能和第二功能，第二代码 代码包括第三个功能。 该方法包括在前导线和尾线（104）中运行第一功能; 在单个线程（106）中运行第三个函数，前导线程调用第三个函数并在前导线程和后退线程（108）中运行第二个函数，第三个函数调用第二个函数。 本公开提供了一种用于处理功能调用的机制，其中SRMT功能和二进制功能可以彼此调用，而不管被叫方功能是SRMT功能还是二进制功能，从而基于运行时信息和用户动态调整可靠性和性能权衡 可选择的政策。

公开(公告)号：US20070079304A1

公开(公告)日：2007-04-05

申请号：US11241610

申请日：2005-09-30

申请人： Bixia Zheng ,  Cheng Wang ,  Ho-seop Kim ,  Mauricio Breternitz ,  Youfeng Wu

发明人： Bixia Zheng ,  Cheng Wang ,  Ho-seop Kim ,  Mauricio Breternitz ,  Youfeng Wu

IPC分类号： G06F9/45

CPC分类号： G06F9/45516 ,  G06F8/443

摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

摘要翻译： 一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。 在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。 在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。 在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。 在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。 描述和要求保护其他实施例。

公开(公告)号：US20160116964A1

公开(公告)日：2016-04-28

申请号：US14986677

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38

CPC分类号： G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US20160116963A1

公开(公告)日：2016-04-28

申请号：US14986676

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

摘要翻译： 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US09152417B2

公开(公告)日：2015-10-06

申请号：US13996610

申请日：2011-09-27

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/45 ,  G06F9/30 ,  G06F9/455 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F8/434 ,  G06F8/4441 ,  G06F9/3834 ,  G06F9/45516

摘要： Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.

摘要翻译： 本文描述了装置，计算机实现的方法，系统和计算机可读介质的实施例，用于加速执行时间存储器别名检查。 可以接收或检索针对执行处理器执行的指令序列。 执行处理器可以包括多个别名寄存器和被配置为检查别名寄存器中的条目以用于存储器混叠的电路。 可以对所接收或检索的指令序列执行一个或多个优化，以优化所接收或检索的指令序列的执行性能。 这可以包括在接收或检索的指令序列中的多个存储器指令的重排序。 在优化之后，可以在优化的指令序列中插入一个或多个移动指令以在执行期间移动别名寄存器中的一个或多个条目，以在执行时加速别名检查。 可以描述和/或要求保护其他实施例。