公开(公告)号：US07965096B2

公开(公告)日：2011-06-21

申请号：US12631992

申请日：2009-12-07

申请人： Chi-Feng Huang

发明人： Chi-Feng Huang

IPC分类号： G01R31/26

CPC分类号： G01R31/2635

摘要： A circuit for detecting faulty diode is disclosed, wherein the circuit for detecting faulty diode comprises a diode having an anode connecting to a voltage supply; a first switch having a first end connected to a cathode of the diode; a testing current source connected to the second end of the first switch; a one-shot circuit connected to a control end of the first switch, by which an output signal is generated and transmitted to the control end; and a comparator connected to a reference voltage input terminal for receiving a reference voltage and connected to the second end of the first switch. When the one-shot circuit closes the first switch for a maintaining period to urge the comparator comparing the reference voltage with the voltage applied to the second end of the first switch, whereby a signal used to discriminate whether the diode is fail or not is generated.

摘要翻译： 公开了一种用于检测故障二极管的电路，其中用于检测故障二极管的电路包括具有连接到电压源的阳极的二极管; 第一开关，其具有连接到所述二极管的阴极的第一端; 连接到第一开关的第二端的测试电流源; 连接到第一开关的控制端的单触发电路，通过该单端电路产生输出信号并将其发送到控制端; 以及连接到参考电压输入端子的比较器，用于接收参考电压并连接到第一开关的第二端。 当单稳态电路将第一开关闭合一段维持时间以促使比较器比较参考电压与施加到第一开关第二端的电压，从而产生用于鉴别二极管是否失败的信号 。

公开(公告)号：US06559493B2

公开(公告)日：2003-05-06

申请号：US10167864

申请日：2002-06-11

申请人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

发明人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

IPC分类号： H01L31119

CPC分类号： H01L28/90 ,  Y10S438/957

摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

摘要翻译： 在第一电介质层中形成第一金属插头。 产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。 第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。 电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。 在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

公开(公告)号：USD467259S1

公开(公告)日：2002-12-17

申请号：US29153257

申请日：2001-10-29

申请人： Hsien-Che Hung ,  Chi-Feng Huang

设计人： Hsien-Che Hung ,  Chi-Feng Huang

公开(公告)号：USD466541S1

公开(公告)日：2002-12-03

申请号：US29153904

申请日：2001-10-29

申请人： Chung-Da Yang ,  Chi-Feng Huang

设计人： Chung-Da Yang ,  Chi-Feng Huang

公开(公告)号：US10269658B2

公开(公告)日：2019-04-23

申请号：US13539027

申请日：2012-06-29

申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

IPC分类号： H01L27/07 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/085 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93 ,  H01L29/06

摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

公开(公告)号：US08796748B2

公开(公告)日：2014-08-05

申请号：US13570157

申请日：2012-08-08

申请人： Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

发明人： Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

IPC分类号： H01L29/80 ,  H01L29/808 ,  H01L29/768 ,  H01L29/78 ,  H01L27/098 ,  H01L27/146 ,  H01L21/28

CPC分类号： H01L27/14614 ,  H01L27/14616 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/7838

摘要： Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.

摘要翻译： 公开了晶体管，其制造方法和图像传感器电路。 在一个实施例中，晶体管包括设置在工件中的掩埋沟道，设置在掩埋沟道上方的栅极电介质和设置在栅极电介质上的栅极层。 栅极层在晶体管的俯视图中包括I形状。

公开(公告)号：US20130299919A1

公开(公告)日：2013-11-14

申请号：US13471270

申请日：2012-05-14

申请人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

发明人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

摘要翻译： 器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。 漏极区域和源极区域设置在栅电极的相对侧上。 绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。 介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。 漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

公开(公告)号：US08558228B2

公开(公告)日：2013-10-15

申请号：US12915757

申请日：2010-10-29

申请人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu ,  Sally Liu

发明人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu ,  Sally Liu

IPC分类号： H01L23/58

CPC分类号： H01L23/5223 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.

摘要翻译： 一种器件包括第一MOM电容器; 第二MOM电容器直接在第一MOM电容器上方并垂直重叠，其中第一和第二MOM电容器中的每一个包括多个并联电容指; 电耦合到第一MOM电容器的第一和第二端口; 以及电耦合到第二MOM电容器的第三和第四端口。 第一，第二，第三和第四端口设置在相应晶片的表面。

公开(公告)号：US20120187494A1

公开(公告)日：2012-07-26

申请号：US13013677

申请日：2011-01-25

申请人： Chi-Feng Huang ,  Chia-Chung Chen

发明人： Chi-Feng Huang ,  Chia-Chung Chen

IPC分类号： H01L27/088 ,  H01L21/66

CPC分类号： H01L29/66174 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/93 ,  H01L29/94

摘要： Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

摘要翻译： 公开了一种用于MOS可变电抗器结构的装置和方法。提供一种装置，包括限定在半导体衬底的一部分中的有源区; 在有源区域中延伸到半导体衬底中的掺杂阱区; 在所述掺杂阱区域上平行布置的至少两个栅极结构; 源极和漏极区域，设置在形成在栅极结构的相对侧上的阱区域中; 栅极连接器，形成在覆盖所述至少两个栅极结构并电耦合所述至少两个栅极结构的第一金属层中; 源极和漏极连接器，其形成在第二金属层中并电耦合到源极和漏极区域; 以及将第二金属层中的源极和漏极连接器与形成在第一金属层中的栅极连接器分开的层间电介质材料。 公开了形成结构的方法。

公开(公告)号：US20110047614A1

公开(公告)日：2011-02-24

申请号：US12461635

申请日：2009-08-19

申请人： Chi-Feng Huang ,  Yuan-Lin Chiang

发明人： Chi-Feng Huang ,  Yuan-Lin Chiang

IPC分类号： G06F12/14

CPC分类号： G06F21/604 ,  G06F21/6209 ,  G06F21/6281 ,  G06F2221/2141

摘要： The invention discloses a permission management system for data accessing and a method thereof, applicable to operating system. The method of permission management for accessing data comprises the steps of: first, monitoring an unoccupied drive letter in operating system; then, detecting a drive letter request event and actively executing an authorizing procedure to produce an access right of the drive letter; and stop monitoring the drive letter and allowing a user to access data corresponding to the drive letter according to the access right.

摘要翻译： 本发明公开了一种适用于操作系统的数据访问权限管理系统及其方法。 访问数据的权限管理方法包括以下步骤：首先，监视操作系统中未占用的驱动器号; 然后，检测驱动器盘符请求事件并主动执行授权过程以产生驱动器盘符的访问权限; 并停止监视驱动器盘符，并允许用户根据访问权限访问与驱动器号相对应的数据。