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    MOS Devices with Mask Layers and Methods for Forming the Same
    4.
    发明申请
    MOS Devices with Mask Layers and Methods for Forming the Same 有权
    具有掩模层的MOS器件及其形成方法

    公开(公告)号：US20130299919A1

    公开(公告)日：2013-11-14

    申请号：US13471270

    申请日：2012-05-14

    申请人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

    发明人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66492 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

    摘要翻译： 器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。 漏极区域和源极区域设置在栅电极的相对侧上。 绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。 介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。 漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

    MOS devices with mask layers and methods for forming the same
    5.
    发明授权
    MOS devices with mask layers and methods for forming the same 有权
    具有掩模层的MOS器件及其形成方法

    公开(公告)号：US09159802B2

    公开(公告)日：2015-10-13

    申请号：US13471270

    申请日：2012-05-14

    申请人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

    发明人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66

    CPC分类号： H01L29/66492 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

    摘要翻译： 器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。 漏极区域和源极区域设置在栅电极的相对侧上。 绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。 介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。 漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

    Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices
    6.
    发明授权
    Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices 有权
    双DNW隔离结构，用于降低高压半导体器件的RF噪声

    公开(公告)号：US08921978B2

    公开(公告)日：2014-12-30

    申请号：US13347031

    申请日：2012-01-10

    申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Hsiao-Chun Lee

    发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Hsiao-Chun Lee

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L27/0928

    摘要： An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.

    摘要翻译： 半导体器件中的隔离结构吸收电子噪声并防止衬底漏电流到达其它器件和信号。 隔离结构提供了围绕RF器件或其他电子噪声源的深N阱（“DNW”）隔离结构的二元性。 DNW隔离结构在至少约2.5μm的深度延伸到衬底中，并且可以耦合到VDD。 在一些实施例中还提供了P +保护环，并且设置在双DNW隔离结构内部，外部或之间。

    Integrated Circuit Devices with Well Regions and Methods for Forming the Same
    7.
    发明申请
    Integrated Circuit Devices with Well Regions and Methods for Forming the Same 审中-公开
    具有井区的集成电路器件及其形成方法

    公开(公告)号：US20140001518A1

    公开(公告)日：2014-01-02

    申请号：US13539027

    申请日：2012-06-29

    申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

    发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

    IPC分类号： H01L27/07 ,  H01L21/8249

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/07 ,  H01L27/085 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/732 ,  H01L29/7327 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93

    摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

    摘要翻译： 一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。 阱区和第一栅极是与第一导电类型相反的第二导电类型。 执行注入以在第一栅极上形成第一导电类型的沟道区。 植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。 进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。 源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20110156161A1

    公开(公告)日：2011-06-30

    申请号：US12648873

    申请日：2009-12-29

    申请人： Kun-Szu Tseng ,  Cheng-Wen Fan ,  Chih-Yu Tseng ,  Victor Chiang Liang

    发明人： Kun-Szu Tseng ,  Cheng-Wen Fan ,  Chih-Yu Tseng ,  Victor Chiang Liang

    IPC分类号： H01L27/06 ,  H01L21/8234

    CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.

    摘要翻译： 提供了包括衬底，第一器件，第二器件和层间介电层的半导体器件。 衬底具有第一区域和第二区域。 第一器件设置在衬底的第一区域中，并且包括在衬底上的第一介电层和第一介电层上的金属栅极。 第二器件位于衬底的第二区域中，并且在衬底上包括第二电介质层，以及在第二介电层上的多晶硅层。 注意，多晶硅层的高度小于第一器件的金属栅极的高度。 层间绝缘层覆盖第二器件。