公开(公告)号：US07595690B2

公开(公告)日：2009-09-29

申请号：US12078844

申请日：2008-04-07

申请人： Ko-Yang Tso ,  Keh-La Lin ,  Yann-Hsiung Liang ,  Chin-Chieh Chao

发明人： Ko-Yang Tso ,  Keh-La Lin ,  Yann-Hsiung Liang ,  Chin-Chieh Chao

IPC分类号： H03F3/26

CPC分类号： H03F3/45219 ,  H03F3/3022 ,  H03F3/45183 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45134 ,  H03F2203/45626 ,  H03F2203/45636

摘要： A voltage-clamping device used in an operational amplifier is provided. The operational amplifier comprises a first transistor. The cross-voltage between the gate and the source of the first transistor is near to a specific voltage and the cross-voltage between the drain and the source of the first transistor is not equal to zero, so as to generate a big substrate current. The voltage-clamping device comprises a second transistor whose source and gate are respectively coupled to the drain of the first transistor and used for receiving a bias signal, so that the second transistor is biased in saturation region, and the voltage at the source of the second transistor is made equal to the difference between the bias signal and the threshold voltage of the second transistor. Thus, the cross-voltage between the drain and the source of the first transistor is reduced and the substrate current is reduced accordingly.

摘要翻译： 提供了一种用于运算放大器的电压钳位装置。 运算放大器包括第一晶体管。 第一晶体管的栅极和源极之间的交叉电压接近特定电压，并且第一晶体管的漏极和源极之间的交叉电压不等于零，以便产生大的衬底电流。 电压钳位装置包括第二晶体管，其源极和栅极分别耦合到第一晶体管的漏极并用于接收偏置信号，使得第二晶体管被偏置在饱和区域中，并且源极处的电压 使第二晶体管等于偏置信号和第二晶体管的阈值电压之间的差。 因此，第一晶体管的漏极和源极之间的交叉电压减小，并且衬底电流相应地减小。

公开(公告)号：US20080260090A1

公开(公告)日：2008-10-23

申请号：US12078604

申请日：2008-04-02

申请人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

发明人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

IPC分类号： G11C19/00

CPC分类号： G11C19/00

摘要： A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.

摘要翻译： 提供了一种用于数据驱动器的移位寄存器。 移位寄存器包括移位寄存单元。 移位寄存单元有选择地接收时钟信号。 移位寄存单元包括触发器; 和第一选择电路。 第一选择电路根据第一选择信号选择性地将时钟信号发送到触发器，其中在触发器接收到使能的数据信号之前，第一选择电路根据触发器将时钟信号发送到触发器 第一选择信号，使得触发器根据时钟信号正确地输出使能的数据信号。

公开(公告)号：US20080253500A1

公开(公告)日：2008-10-16

申请号：US12073197

申请日：2008-03-03

申请人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

发明人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

IPC分类号： G11C19/00 ,  H03K3/289

CPC分类号： H03K3/35625 ,  H03K3/356156

摘要： A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

摘要翻译： 提供了一个触发器。 触发器用于源驱动器中的移位寄存器。 触发器用于接收第一时钟信号，输入信号并输出​​输出信号。 输出信号反馈给触发器。 触发器包括用于接收输入信号并输出​​输出信号的触发器芯。 当输入信号和输出信号都被禁用时，触发器内核被禁用。 当输入信号或输出信号被使能时，触发器使能使能输出输出信号。

公开(公告)号：US20080252667A1

公开(公告)日：2008-10-16

申请号：US12078993

申请日：2008-04-09

申请人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

发明人： Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

IPC分类号： G09G5/10 ,  H03M1/66

CPC分类号： H03M1/765 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2320/0276

摘要： A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly.

摘要翻译： 数模（D / A）转换器包括解码器装置和运算放大器。 解码器装置包括第一和第二解码器单元。 第一解码器单元响应于设置的第一灰度级的值选择第一电压的电压作为第一和第二电压。 第二解码器单元响应于分别设置的第二灰度级的最大值和最小值，选择作为第一和第二电压的第一电压和第二电压的第一电压和第二边界电压作为第一和第二电压。 第二解码器单元还响应于第二灰度级的中间值，分别选择第一和第二边缘电压作为第一和第二电压。 运算放大器相应地产生具有在第一和第二电压之间的电平的像素电压。

公开(公告)号：US08736372B2

公开(公告)日：2014-05-27

申请号：US13435322

申请日：2012-03-30

申请人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

发明人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

IPC分类号： H03F3/45 ,  G06F3/038

CPC分类号： H03F3/45183 ,  G09G3/3674 ,  G09G2310/0291

摘要： An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.

摘要翻译： 公开了一种源驱动器的输出缓冲器。 输出缓冲器包括缓冲器输入，缓冲器输出，差分输入级，偏置电流源，输出级，补偿电容和比较器。 输出级和比较器均在模拟电源电压（AVDD）和一半模拟电源电压（HAVDD）之间运行，或两者在半模拟电源电压（HAVDD）和接地电压之间运行。 比较器将输入信号与输出信号进行比较，并根据比较结果向偏置电流源输出控制信号。

公开(公告)号：US20120306828A1

公开(公告)日：2012-12-06

申请号：US13484801

申请日：2012-05-31

申请人： Li-Ping Lin ,  Ko-Yang Tso ,  Chi-Yuan Lu ,  Chin-Chieh Chao ,  Yu-Lung Lo

发明人： Li-Ping Lin ,  Ko-Yang Tso ,  Chi-Yuan Lu ,  Chin-Chieh Chao ,  Yu-Lung Lo

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3688

摘要： The invention provides a driving circuit applied in a LCD apparatus and operating method thereof. The driving circuit includes at least one first channel, at least one second channel, a timing controller, and a panel driver. The timing controller includes a digital signal switching unit. The digital signal switching unit selectively performs a polarity exchange to a first digital data signal and a second digital data signal according to a control signal. The panel driver includes an analog signal switching unit. The analog signal switching unit performs a switching corresponding to the polarity exchange according to the control signal to make the driving circuit selectively operated under a first operation mode or a second operation mode.

摘要翻译： 本发明提供一种应用于LCD装置的驱动电路及其操作方法。 驱动电路包括至少一个第一通道，至少一个第二通道，定时控制器和面板驱动器。 定时控制器包括数字信号切换单元。 数字信号切换单元根据控制信号有选择地执行与第一数字数据信号和第二数字数据信号的极性交换。 面板驱动器包括模拟信号切换单元。 模拟信号切换单元根据控制信号执行与极性交换相对应的切换，以使得驱动电路在第一操作模式或第二操作模式下选择性地操作。

公开(公告)号：US08233253B2

公开(公告)日：2012-07-31

申请号：US12427525

申请日：2009-04-21

申请人： Chih-Chuan Huang ,  Hui-Wen Miao ,  Ko-Yang Tso

发明人： Chih-Chuan Huang ,  Hui-Wen Miao ,  Ko-Yang Tso

IPC分类号： H02H9/00

CPC分类号： H02H3/22 ,  H02H3/066

摘要： The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

摘要翻译： 本发明公开了一种电子系统中信号输出电路的控制装置。 控制装置包括检测电路，开关和控制电路。 检测电路用于检测电子系统是否具有异常状态。 开关电连接在信号接收端和信号输出电路之间。 控制电路电连接在检测电路和开关之间。 一旦检测电路检测到电子系统处于异常状态，控制电路将开关置于高阻态。

公开(公告)号：US20110122102A1

公开(公告)日：2011-05-26

申请号：US12900236

申请日：2010-10-07

申请人： Ko-Yang Tso ,  Hui-Wen Miao ,  Yu-Lung Lo ,  Yann-Hsiung Liang ,  Hsin-Yeh Wu

发明人： Ko-Yang Tso ,  Hui-Wen Miao ,  Yu-Lung Lo ,  Yann-Hsiung Liang ,  Hsin-Yeh Wu

IPC分类号： G06F3/038

CPC分类号： G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291

摘要： An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage.

摘要翻译： 提供包括第一开关电路和缓冲器的输出缓冲器。 第一开关电路接收第一和第二输入信号。 缓冲电路包括第一和第二输入级，第一和第二输出级和第二开关电路。 第一和第二输入级耦合到第一开关电路。 第一和第二输出级耦合到第二开关电路。 耦合到第一和第二输入级以及第一和第二输出级的第二开关电路选择性地将第一和第二输入级之一耦合到第一输出级，并且将另一个输入级选择性地耦合到第二输出级。 第一开关电路还选择性地将第一和第二输入信号之一提供给第一输入级，并且选择性地将另一个提供给第二输入级。

公开(公告)号：US20090179326A1

公开(公告)日：2009-07-16

申请号：US12106148

申请日：2008-04-18

申请人： Ko-Yang Tso ,  Chung-Cheng Chou ,  William Wang ,  Chia-Hung Hsu

发明人： Ko-Yang Tso ,  Chung-Cheng Chou ,  William Wang ,  Chia-Hung Hsu

IPC分类号： H01L23/49

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a semiconductor device package. The package includes a chip disposed on a supported board and a conductive path formed between the chip and the supported board, on the backside of the supported board, or on the chip, so that the conductive path does not have to go around a region where the chip is located. Accordingly, the dimensions of the semiconductor device package are reduced.

摘要翻译： 本发明提供一种半导体器件封装。 该封装包括设置在支撑板上的芯片和形成在芯片和支撑板之间，支撑板的背面或芯片上的导电路径，使得导电路径不必绕过 芯片位于。 因此，半导体器件封装的尺寸减小。

公开(公告)号：US20080180425A1

公开(公告)日：2008-07-31

申请号：US12010354

申请日：2008-01-24

申请人： Yong-Nien Rao ,  Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

发明人： Yong-Nien Rao ,  Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

IPC分类号： G09G5/00

CPC分类号： G09G3/20 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2310/0245 ,  G09G2310/0275 ,  G09G2320/0233

摘要： A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.

摘要翻译： 上电屏幕图案校正装置用于校正源驱动器的输出端的开始输出数据，使得显示器的开机屏幕图案基本上均匀。 校正装置包括触发器，第一逻辑单元和第二逻辑单元。 触发器响应于低电平的功率启动信号而控制内部信号的电平基本上等于低信号电平。 第一逻辑单元响应于内部信号的低电平或高电平的高阻抗控制信号而启用第一信号。 第二逻辑单元启用第二信号，使得输出端耦合到电荷共享线，并且电源屏幕图案响应于内部信号的低电平或电荷共享控制信号的低电平而均匀 。