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110 条记录 (耗时 0.029 秒)

    Gain calibration of a digital controlled oscillator
    21.
    发明申请
    Gain calibration of a digital controlled oscillator 有权
    增益数字控制振荡器的校准

    公开(公告)号：US20060033582A1

    公开(公告)日：2006-02-16

    申请号：US11149859

    申请日：2005-06-10

    申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

    发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

    摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

    摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

    Image reject filtering in a direct sampling mixer
    23.
    发明申请
    Image reject filtering in a direct sampling mixer 审中-公开
    直接采样混频器中的图像抑制滤波

    公开(公告)号：US20050233725A1

    公开(公告)日：2005-10-20

    申请号：US10828386

    申请日：2004-04-20

    申请人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

    发明人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

    IPC分类号： H03D7/18 ,  H03H19/00 ,  H04B1/16 ,  H04B1/28

    CPC分类号： H03D7/18 ,  H03H19/004 ,  H03H2007/0192

    摘要： Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

    摘要翻译： 公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。 公开了在信号处理系统的同相和正交分支中使用旋转电容器。 在I和Q通道的分支之间的信息交换被用于实现复杂的过滤器。 还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。

    Type-II All-Digital Phase-Locked Loop (PLL)
    24.
    发明申请
    Type-II All-Digital Phase-Locked Loop (PLL) 有权
    II型全数字锁相环（PLL）

    公开(公告)号：US20060290435A1

    公开(公告)日：2006-12-28

    申请号：US11464420

    申请日：2006-08-14

    申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

    发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

    IPC分类号： H03L7/00

    CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

    摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

    摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

    Wireless communications device having type-II all-digital phase-locked loop (PLL)
    25.
    发明申请
    Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
    具有II型全数字锁相环（PLL）的无线通信设备

    公开(公告)号：US20050212606A1

    公开(公告)日：2005-09-29

    申请号：US11122670

    申请日：2005-05-04

    申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

    发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

    IPC分类号： H03F1/02 ,  H03F1/32 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/00

    CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

    摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

    摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

    Sampling mixer with asynchronous clock and signal domains
    26.
    发明申请
    Sampling mixer with asynchronous clock and signal domains 有权
    具有异步时钟和信号域的采样混频器

    公开(公告)号：US20050130618A1

    公开(公告)日：2005-06-16

    申请号：US11028995

    申请日：2005-01-03

    申请人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

    发明人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

    IPC分类号： H03D7/12 ,  H04B1/10 ,  H04B1/06 ,  H04B7/00 ,  H04L7/00

    CPC分类号： H03D7/125 ,  H04B1/1036

    摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

    摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。

    Parallel Redundant Single-Electron Device and Method of Manufacture
    27.
    发明申请
    Parallel Redundant Single-Electron Device and Method of Manufacture 有权
    并联冗余单电子器件及其制造方法

    公开(公告)号：US20080057878A1

    公开(公告)日：2008-03-06

    申请号：US11847008

    申请日：2007-08-29

    申请人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

    发明人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

    IPC分类号： H04B1/40

    CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S977/937

    摘要： A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

    摘要翻译： 一种制造单电子器件的并行冗余阵列的方法。 该方法包括：（a）提供掩模，用于扩散由第一组多个有源区限定的多个n掺杂区，（b）提供掩模，用于设置由第二组 多个暴露区域，其中第一组的多个暴露区域中的第一构件之间的偏移量偏离第二组的多个暴露区域中的第二构件，以及（c）制造并行冗余 作为偏移的函数的单电子器件的阵列。

    Single-Electron Injection/Extraction Device for a Resonant Tank Circuit and Method of Operation Thereof
    30.
    发明申请
    Single-Electron Injection/Extraction Device for a Resonant Tank Circuit and Method of Operation Thereof 有权
    用于谐振槽电路的单电子注入/提取装置及其操作方法

    公开(公告)号：US20080061892A1

    公开(公告)日：2008-03-13

    申请号：US11846987

    申请日：2007-08-29

    申请人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

    发明人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

    IPC分类号： H03B28/00 ,  H04B1/40

    CPC分类号： H03B1/04 ,  H03B5/12 ,  H03B2202/027 ,  H03B2202/076

    摘要： A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.

    摘要翻译： 一种降低谐振回路中相位噪声的系统。 该系统包括被配置为将单个电子注入到振荡器电路槽电路中的单电子器件。 该系统还包括耦合到单电子器件并被配置为使得单电子器件基于谐振的极端（最大或最小）电特性输出的相位将单个电子注入到谐振回路中的同步器 坦克回路。