公开(公告)号：US06041328A

公开(公告)日：2000-03-21

申请号：US992619

申请日：1997-12-17

Applicant: Ching Yu

Inventor： Ching Yu

IPC: H04L12/56 ,  G06F17/30

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901

Abstract: The present invention keeps track of available elements in a list of elements available to a given device for processing from an index and count mechanism. Such an index and count mechanism provides an index that indicates a starting element in the list of elements that is available to the given device for processing. Such an index and count mechanism also provides a count that indicates a subsequent number of elements, from the starting element in the list of elements, that are available to the given device for processing. A first index register and a second index register alternately keep track of a last available element in the list of elements available to be processed by the given device until the last available element is a very last element in the list of elements. In addition, the first index register and the second index register also alternately keep track of a current element, in the list of elements, that is currently being processed by the given device until the very last element in the list of elements has been processed by the given device. By thus alternating between the first and second index registers for keeping track of the last available element and by thus alternating between the first and second index registers for keeping track of the currently processed element, processing through multiple cycles of the list of elements may be kept track of in a simple manner. The present invention may be used to particular advantage when the given device is a computer network peripheral device that processes descriptors within a shared memory of a host computer system.

Abstract translation: 本发明在索引和计数机制中跟踪给定设备可用的元素列表中的可用元素以进行处理。 这样的索引和计数机制提供了一个索引，该索引指示给定设备可用于处理的元素列表中的起始元素。 这样的索引和计数机制还提供了一个计数，其指示从给定设备可用于处理的元素列表中的起始元素的后续数量的元素。 第一索引寄存器和第二索引寄存器交替地跟踪可用于由给定设备处理的元素的列表中的最后可用元素，直到最后一个可用元素是元素列表中的最后一个元素。 此外，第一索引寄存器和第二索引寄存器还交替地跟踪当前由给定设备处理的元素列表中的当前元素，直到元素列表中的最后一个元素已经被处理 给定的设备。 通过这样在第一和第二索引寄存器之间交替以便跟踪最后一个可用元素，并且通过在第一和第二索引寄存器之间交替来跟踪当前处理的元件，可以保持元素列表的多个周期的处理 轨道以简单的方式。 当给定设备是处理主计算机系统的共享存储器内的描述符的计算机网络外围设备时，本发明可以被用于特别的优点。

公开(公告)号：US08131895B2

公开(公告)日：2012-03-06

申请号：US12754495

申请日：2010-04-05

Applicant: Steven L. Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steven L. Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F5/00 ,  H03K19/00

CPC classification number: G06F13/24 ,  G06F13/385 ,  G06F13/4282

Abstract: Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The wakeup event identifies the individual event queue. The host subsystem, in response to retrieval of the wakeup event from the intermediary event queue, activates an individual event handler to consume events from the individual event queue.

Abstract translation: 管理主机子系统和外围设备之间的交互的方法。 粗略描述，外围设备将事件写入单个事件队列中，并且与之结合，还将唤醒事件写入中间事件队列。 唤醒事件标识单个事件队列。 响应于从中间事件队列检索唤醒事件，主机子系统激活单个事件处理程序以从各个事件队列消耗事件。

公开(公告)号：US07769923B2

公开(公告)日：2010-08-03

申请号：US11050476

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F3/00 ,  G06F13/28

CPC classification number: G06F13/24 ,  G06F13/385 ,  G06F13/4282

Abstract: Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The wakeup event identifies the individual event queue. The host subsystem, in response to retrieval of the wakeup event from the intermediary event queue, activates an individual event handler to consume events from the individual event queue.

Abstract translation: 管理主机子系统和外围设备之间的交互的方法。 粗略描述，外围设备将事件写入单个事件队列中，并且与之结合，还将唤醒事件写入中间事件队列。 唤醒事件标识单个事件队列。 响应于从中间事件队列检索唤醒事件，主机子系统激活单独的事件处理程序以从各个事件队列消耗事件。

公开(公告)号：US07596644B2

公开(公告)日：2009-09-29

申请号：US11329444

申请日：2006-01-11

Applicant: Ching Yu ,  David Riddoch ,  Steve Pope ,  John Mingyung Chiang ,  Alok Singh ,  Derek Roberts

Inventor： Ching Yu ,  David Riddoch ,  Steve Pope ,  John Mingyung Chiang ,  Alok Singh ,  Derek Roberts

IPC: G06F3/00

CPC classification number: G06F13/28

Abstract: System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.

Abstract translation: 描述了用于通过速率起搏多个队列来为不同连接量身定制的不同传输速率的步调引擎的系统和方法。 粗略地描述，速度引擎包括用于从发送DMA队列管理器接收队列的分档控制器，并且确定在工作仓，快速仓或慢速仓中存储和起搏的特定队列的最早允许时间。 步速表存储关于耦合到发送DMA队列管理器的每个连接的最小间隔间隔的信息。 定时器与具有多位连续计数器的分箱控制器耦合，该计数器以预定时间单位递增并在预定时间量之后卷绕。

公开(公告)号：US07562366B2

公开(公告)日：2009-07-14

申请号：US11050483

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts ,  John Mingyung Chiang

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts ,  John Mingyung Chiang

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901

Abstract: Method for managing a data transmit queue, for use with a host and a network interface device. Roughly described, the host writes data buffer descriptors into a transmit descriptor queue, and the network interface device writes events to notify the host when it has completed processing of a transmit data buffer. Each of the transmit completion event descriptors notify the host of completion of a plurality of the transmit data buffers.

Abstract translation: 用于管理与主机和网络接口设备一起使用的数据传输队列的方法。 大致描述，主机将数据缓冲区描述符写入发送描述符队列，并且网络接口设备写入事件以在完成处理发送数据缓冲区时通知主机。 每个发送完成事件描述符通知主机多个发送数据缓冲器的完成。

公开(公告)号：US07496699B2

公开(公告)日：2009-02-24

申请号：US11156228

申请日：2005-06-17

Applicant: Steve L. Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

Inventor： Steve L. Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

IPC: G06F3/00 ,  G06F13/28 ,  G06F12/00

CPC classification number: H04L49/901 ,  G06F13/28 ,  G06F13/385 ,  H04L49/90

Abstract: Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

Abstract translation: 用于从主机存储器检索缓冲器描述符以供外围设备使用的方法和装置。 在一个实施例中，诸如NIC的外围设备包括多个缓冲区描述符缓存，每个对应于多个主机存储器描述符队列中的相应一个的多个缓冲区描述符缓存，以及多个队列描述符，每个对应于主机存储器描述符 队列 每个队列描述符包括用于对应的描述符队列的主机存储器读地址指针，并且该相同的读指针用于从算法上导出描述符高速缓存写地址，在该地址处写入从相应主机存储器描述符队列检索的缓冲器描述符。

公开(公告)号：US06732184B1

公开(公告)日：2004-05-04

申请号：US09604266

申请日：2000-06-26

Applicant: Shashank Merchant ,  Ching Yu

Inventor： Shashank Merchant ,  Ching Yu

IPC: G06F1300

CPC classification number: H04L45/00 ,  H04L45/742

Abstract: A switching system includes a multiport module having an address table for storing network addresses, and a host processor configured for selectively swapping the stored network addresses in the address table to an internal memory that serves as an overflow address table for the multiport switch module. The address table internal to the multiport module is configured for storing a prescribed number of network addresses for high-speed access, for example the most frequently-used network addresses. The host processor, configured for controlling the storage of network addresses between the address table and the external memory, uses the external memory as the overflow address table for storage of less frequently-used network addresses, for example addresses of network devices that transmit little more than periodic “keep-alive” frames. Hence, a large number of addresses may be managed by the switching system, without the necessity of an unusually large on-chip address table.

Abstract translation: 交换系统包括具有用于存储网络地址的地址表的多端口模块，以及被配置为将地址表中存储的网络地址有选择地交换到用作多端口交换模块的溢出地址表的内部存储器的主处理器。 多端口模块内部的地址表被配置为存储用于高速访问的规定数量的网络地址，例如最常用的网络地址。 配置为控制地址表和外部存储器之间的网络地址存储的主处理器使用外部存储器作为用于存储较不频繁使用的网络地址的溢出地址表，例如，传输更多的网络设备的地址 比定期的“保持活动”框架。 因此，可以由交换系统管理大量地址，而不需要非常大的片上地址表。

公开(公告)号：US06535489B1

公开(公告)日：2003-03-18

申请号：US09315854

申请日：1999-05-21

Applicant: Shashank Merchant ,  Robert Williams ,  John M. Chiang ,  Ching Yu

Inventor： Shashank Merchant ,  Robert Williams ,  John M. Chiang ,  Ching Yu

IPC: G06F1110

CPC classification number: H04L45/245 ,  H04L41/0654 ,  H04L43/0817 ,  H04L45/28 ,  Y02D50/30

Abstract: A network switch configured for switching data packets across multiple ports and for supporting trunked data paths uses an address table to generate frame forwarding information. When a link in a trunked data path experiences a change in its operating status, the trunk data path is reconfigured to reflect the current operating conditions, without reprogramming the address table or powering down the switch.

Abstract translation: 配置为跨多个端口切换数据包并支持集群数据路径的网络交换机使用地址表来生成帧转发信息。 当中继数据路径中的链路经历其操作状态的改变时，重新配置中继线数据路径以反映当前的工作状态，而不重新编程地址表或关闭交换机。

公开(公告)号：US06340898B1

公开(公告)日：2002-01-22

申请号：US08993122

申请日：1997-12-18

Applicant: Pierre Haubursin ,  Ching Yu

Inventor： Pierre Haubursin ,  Ching Yu

IPC: H03K19173

CPC classification number: H03K19/1731

Abstract: An output driver that may be configured to operate as a totem-pole driver, or as an open-drain driver. The output driver comprises a totem-pole driver coupled to an output pin. A control circuit is coupled to the output enable input of the totem-pole driver. The control circuit is supplied with an open-drain control signal controlled by the user interface. When the open-drain control signal is at a first logic level, the output driver operates as an open-drain driver. When the open-drain control signal is at a second logic level, the output driver is configured to operate as a totem-pole driver.

Abstract translation: 可以配置为作为图腾柱驱动器或作为开漏驱动器运行的输出驱动器。 输出驱动器包括耦合到输出引脚的图腾柱驱动器。 控制电路耦合到图腾柱驱动器的输出使能输入。 该控制电路具有由用户接口控制的开漏控制信号。 当开漏控制信号处于第一逻辑电平时，输出驱动器作为开漏驱动器工作。 当开漏控制信号处于第二逻辑电平时，输出驱动器被配置为作为图腾柱驱动器工作。

公开(公告)号：US06317847B1

公开(公告)日：2001-11-13

申请号：US09144644

申请日：1998-08-31

Applicant: Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

Inventor： Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

IPC: G06F1100

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3648

Abstract: A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Abstract translation: 在网络接口中提供了用于跟踪对所选寄存器的读和写访问的系统。 该系统具有一个读取跟踪寄存器，每个寄存器包含一个独立的位，用于监视外部CPU进行读取访问。 写入跟踪寄存器为每个待监视的寄存器提供一个位，以便CPU进行写访问。 当CPU对被监视的寄存器执行读或写访问时，从CPU解码地址信号的解码器产生提供给读跟踪寄存器和/或写跟踪寄存器的跟踪选择信号。 响应于跟踪选择信号，表示被监视寄存器的位被设置为预定的逻辑状态，指示所监视的寄存器被CPU访问以用于读取和/或写入。