-
公开(公告)号：US20180374487A1
公开(公告)日：2018-12-27
申请号：US16017072
申请日：2018-06-25
Inventor： John Paul LESSO
Abstract: Detecting a replay attack on a voice biometrics system comprises receiving a speech signal; forming an autocorrelation of at least a part of the speech signal; and identifying that the received speech signal may result from a replay attack based on said autocorrelation. Identifying that the received speech signal may result from a replay attack may be achieved by: comparing the autocorrelation with a reference value; and identifying that the received speech signal may result from a replay attack based on a result of the comparison of the autocorrelation with the reference value, or by: supplying the autocorrelation to a neural network trained to distinguish autocorrelations formed from speech signals resulting from replay attacks from autocorrelations formed from speech signals not resulting from replay attacks.
-
公开(公告)号：US20180288546A1
公开(公告)日：2018-10-04
申请号：US15935542
申请日：2018-03-26
Inventor： John Paul LESSO , Emmanuel Philippe Christian HARDY
CPC classification number: H04R29/004 , G01N29/42 , G01N29/4427 , G01N29/46 , H04R3/00 , H04R19/005 , H04R2410/03
Abstract: This application describes an apparatus (300) for monitoring for blockage of an acoustic (110) port of a microphone device (100). The apparatus has a spectrum peak detect block (301) for receiving a microphone signal (SMIC) and determining, from the microphone signal, a resonance frequency (fH) and a quality factor (QH) of a resonance (202) associated with the acoustic port. A condition monitoring block (302) is configured to determine any change in resonance frequency and quality factor and to determine a blockage status for the microphone based on said detect changes. The condition monitoring block identifies a change in blockage status if there is a change in quality factor.
-
公开(公告)号：US20170194926A1
公开(公告)日：2017-07-06
申请号：US15466661
申请日：2017-03-22
Inventor： John Paul LESSO , Toru IDO
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
-
公开(公告)号：US20170187383A1
公开(公告)日：2017-06-29
申请号：US15384861
申请日：2016-12-20
Inventor： John Paul LESSO
CPC classification number: H03L7/091 , H03L7/085 , H03L7/0891 , H03L7/099 , H03L7/0995 , H03L7/181
Abstract: This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses. Each time-to-digital converter comprises a controlled-oscillator (401, 801) configured so as to operate at a first frequency when the respective adjustment signal is at the first signal level and operate at a second frequency when the respective adjustment signal is at the second signal level and a counter (403) configured to produce a count value of the number oscillations of the controlled-oscillator in each of a succession of count periods defined by a count clock signal. The first and second digital signals are based on the count values output from the respective counters. The difference between the first and second digital signals may be determined and input to digital loop filter (203) before driving numerically-controlled-oscillator (204) to produce the output signal.
-
公开(公告)号：US20160358617A1
公开(公告)日：2016-12-08
申请号：US15243154
申请日：2016-08-22
Inventor： John Paul LESSO , Peter John FRITH , John Laurence PENNOCK
IPC: G10L19/16 , H04L25/49 , G10L19/002
CPC classification number: G10L19/167 , G10L19/002 , H04L25/49 , H04L25/4902 , H04L25/4904
Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator (204). The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon on a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry (202) samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.
Abstract translation: 本申请涉及用于通过单个通信链路（例如单线）传送多个数字数据流，特别是数字音频数据的方法和装置。 该应用描述了包括脉冲长度调制（PLM）调制器（204）的音频接口电路。 PLM响应于多个数据流（PDM-R，PDM-L），以产生一系列数据脉冲（PLM），其中单个数据脉冲具有在多个传输周期中的每一个中定义的上升沿和下降沿 通过第一时钟信号（TCLK）。 每个数据脉冲的上升沿和下降沿的定时取决于来自多个数据流的当前数据样本的组合。 传输窗口中的数据脉冲的持续时间和位置有效地定义了对数据进行编码的数据符号。 还公开了用于接收和提取数据的电路。 接口接收数据脉冲流（PLM），并且数据提取电路（202）对数据脉冲采样以确定脉冲表示哪些可能数据符号，并确定至少一个接收到的数据流的数据值。
-
Patent Agency Ranking
公开(公告)号：US20230244881A1
公开(公告)日：2023-08-03
申请号：US18296297
申请日：2023-04-05
Inventor： John Paul LESSO
CPC classification number: G06G7/48 , H02M1/0845 , H03M1/06 , H03M1/12 , G06N3/065
Abstract: This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.
-
公开(公告)号：US20230058320A1
公开(公告)日：2023-02-23
申请号：US17981170
申请日：2022-11-04
Inventor： Thomas Ivan HARVEY , John Paul LESSO
Abstract: A method for use in a biometric process, comprising: for a first function and a second function, applying an acoustic stimulus to a user's ear; and for the second function: receiving a response signal of a user's ear to the acoustic stimulus; and extracting, from the response signal, one or more features for use in a biometric process, wherein the first function is a function other than to induce the response signal for use in the biometric process.
-
公开(公告)号：US20220329219A1
公开(公告)日：2022-10-13
申请号：US17835326
申请日：2022-06-08
Inventor： John Paul LESSO
IPC: H03F3/217
Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (ε) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.
-
公开(公告)号：US20210385565A1
公开(公告)日：2021-12-09
申请号：US17408630
申请日：2021-08-23
Inventor： John Paul LESSO
Abstract: There is described a switchable microphone device which may be switched between a digital output mode and an analog output mode. There is further described a system for use of such a device, which allows for the switching between analog and digital computing modes.
-
公开(公告)号：US20210192033A1
公开(公告)日：2021-06-24
申请号：US17193430
申请日：2021-03-05
Inventor： John Paul LESSO
IPC: G06F21/32 , G10L17/26 , G06F3/16 , G10L17/24 , H04L29/06 , G10L17/08 , H04K1/00 , G10L25/06 , H04W12/06 , G10L17/00
Abstract: Detecting a replay attack on a voice biometrics system comprises receiving a speech signal; forming an autocorrelation of at least a part of the speech signal; and identifying that the received speech signal may result from a replay attack based on said autocorrelation. Identifying that the received speech signal may result from a replay attack may be achieved by: comparing the autocorrelation with a reference value; and identifying that the received speech signal may result from a replay attack based on a result of the comparison of the autocorrelation with the reference value, or by: supplying the autocorrelation to a neural network trained to distinguish autocorrelations formed from speech signals resulting from replay attacks from autocorrelations formed from speech signals not resulting from replay attacks.
-
-
-
-
-
-
-
-
-
Search Results
151
records
(took 0.021 seconds)
