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公开(公告)号：US11101778B2
公开(公告)日：2021-08-24
申请号：US16740800
申请日：2020-01-13
Inventor： John Paul Lesso , Toru Ido
Abstract: The present disclosure relates to Class D amplifier circuitry comprising: an input for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first supply rail and a second supply rail, and a second driver stage is provided for switching the second node between the first supply rail and the second supply rail. The Class D amplifier circuitry also includes first driver control circuitry configured to receive a first carrier wave and control the switching of the first driver stage based in part on the first carrier wave; second driver control circuitry configured to receive a second carrier wave and control the switching of the second driver stage based in part on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave. A phase shift between the first carrier wave and the second carrier wave is adjustable responsive to a mode control signal.
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公开(公告)号：US10587232B2
公开(公告)日：2020-03-10
申请号：US15982237
申请日：2018-05-17
Inventor： John Paul Lesso , Toru Ido
Abstract: The present disclosure relates to Class D amplifier circuitry comprising: an input for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first supply rail and a second supply rail, and a second driver stage is provided for switching the second node between the first supply rail and the second supply rail. The Class D amplifier circuitry also includes first driver control circuitry configured to receive a first carrier wave and control the switching of the first driver stage based in part on the first carrier wave; second driver control circuitry configured to receive a second carrier wave and control the switching of the second driver stage based in part on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave. A phase shift between the first carrier wave and the second carrier wave is adjustable responsive to a mode control signal.
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公开(公告)号：US09899978B2
公开(公告)日：2018-02-20
申请号：US15466661
申请日：2017-03-22
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
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公开(公告)号：US20160065158A1
公开(公告)日：2016-03-03
申请号：US14836006
申请日：2015-08-26
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
Abstract translation: 本申请涉及D类放大器电路（200）。 调制器（201）基于调制器输入信号（Dm）控制D类输出级（202），以产生代表输入信号（Din）的输出信号（Vout）。 可以包括ADC（207）的误差块（205）从输出信号和输入信号产生误差信号（＆egr）。 在各种实施例中，基于输入信号（Din）的振幅的指示，可以对误差信号（＆egr）贡献于调制器输入信号（Dm）的程度是可变的。 误差信号可以在信号选择器块（203）的第一输入（204）处被接收。 可以在信号选择器块（203）的第二输入（206）处接收输入信号。 信号选择器块可以在第一和第二操作模式下操作，其中在第一模式中，调制器输入信号至少部分地基于误差信号; 并且在第二模式中，调制器输入信号基于数字输入信号，并且与误差信号无关。 误差信号可以用于降低高信号电平的失真，但不会在低信号电平下使用，因此低信号电平的噪声基底不依赖于误差块的分量（205）。
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公开(公告)号：US11918345B2
公开(公告)日：2024-03-05
申请号：US18298573
申请日：2023-04-11
Inventor： John P. Lesso , Yanto Suryono , Toru Ido
CPC classification number: A61B5/0823 , A61B5/0803 , A61B5/6803 , A61B5/7246 , A61B5/725 , A61B5/7264 , A61B5/7275 , A61B2562/0219
Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.
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Patent Agency Ranking
26.发明授权公开(公告)号：US11755894B2
公开(公告)日：2023-09-12
申请号：US16838495
申请日：2020-04-02
Inventor： Gordon James Bates , Toru Ido
CPC classification number: G06N3/063 , G11C11/54 , G11C13/0069 , G11C2013/0078
Abstract: This application relates to methods and apparatus for computing, especially to circuitry for performing computing, at least partly, in the analogue domain. The circuitry (200) comprises a plurality of memory cells (201), each memory cell having first and second paths between an electrode (202) for receiving an input current and respective positive and negative electrodes (203) for outputting a differential-current output. Memristors (101) are located in the first and second paths. The memory cells are configured into sets (205) of memory cells, the memory cells of each said set being connected so as to provide a differential current set output that corresponds to a combination of the cell outputs of all of the memory cells of that set. For each set, at least some of the memory cells of that set are configured to receive a different input current to other memory cells of that set.
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公开(公告)号：US11731163B2
公开(公告)日：2023-08-22
申请号：US16989050
申请日：2020-08-10
Inventor： John P. Lesso , Toru Ido
CPC classification number: B06B1/0207 , H02M3/07 , H10N30/20 , H10N30/802
Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer based on an input signal. The circuitry comprises: primary driver circuitry configured to receive the input signal and to output a primary driving signal to the piezoelectric transducer based on the input signal; and secondary driver circuitry configured to receive an error signal indicative of an error between the input signal and the primary driving signal and to output a secondary driving signal to the piezoelectric transducer based on the error signal, wherein the primary driver circuitry and the secondary driver circuitry both comprise switching converter circuitry.
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公开(公告)号：US11653855B2
公开(公告)日：2023-05-23
申请号：US17541904
申请日：2021-12-03
Inventor： John P. Lesso , Yanto Suryono , Toru Ido
CPC classification number: A61B5/0823 , A61B5/0803 , A61B5/6803 , A61B5/725 , A61B5/7246 , A61B5/7264 , A61B5/7275 , A61B2562/0219
Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.
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公开(公告)号：US11646708B2
公开(公告)日：2023-05-09
申请号：US17113561
申请日：2020-12-07
Inventor： John P. Lesso , Toru Ido
CPC classification number: H03G3/3005 , H03F3/183 , H04R17/00 , H03F2200/03 , H03G2201/103
Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry comprises amplifier circuitry configured to receive a drive signal and to output an output signal, based on the drive signal, to the piezoelectric transducer, a variable capacitor configured to be coupled in series with the piezoelectric transducer, and control circuitry. The control circuitry is configured to control a capacitance of the variable capacitor to compensate for hysteresis in the piezoelectric transducer and to control a gain of the amplifier circuitry to compensate for signal attenuation caused by the variable capacitor.
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公开(公告)号：US11121690B2
公开(公告)日：2021-09-14
申请号：US16552843
申请日：2019-08-27
Inventor： John Paul Lesso , Toru Ido
Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.
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