公开(公告)号：US4460978A

公开(公告)日：1984-07-17

申请号：US322915

申请日：1981-11-19

Applicant: Ching-Lin Jiang ,  David L. Taylor

Inventor： Ching-Lin Jiang ,  David L. Taylor

IPC: G11C14/00 ,  G11C11/40

CPC classification number: G11C14/00

Abstract: A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.cc to a high voltage state to reestablish common threshold voltages for the variable threshold voltage transistors (36, 41).

Abstract translation: 非易失性静态随机存取存储单元（10）包括一对交叉耦合晶体管（12,14），其作为双稳态电路来存储数据状态。 可变阈值晶体管（36,41）分别串联连接在驱动晶体管（12,14）和负载装置（48,50）之间。 控制节点（40）被驱动到高电压状态以使可变阈值晶体管（36,41）中的一个被驱动以具有较高的阈值电压，从而存储保持在交叉耦合晶体管（12）中的数据状态 ，14）。 数据状态因此以非易失性形式存储。 一旦召回，存储器单元（10）被重新激活，并且可变阈值晶体管（36,41）之间的阈值差使得驱动晶体管（12,14）被设置在存储的数据状态。 由存储器单元（10）调用的数据是真实的而不是互补形式。 通过将电源端子Vcc驱动到高电压状态来重建可变阈值晶体管（36,41），以重建可变阈值电压晶体管（36,41）的公共阈值电压。

公开(公告)号：US4308594A

公开(公告)日：1981-12-29

申请号：US117223

申请日：1980-01-31

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/402 ,  G11C11/412 ,  H01L27/108 ,  H01L29/78 ,  H03K3/356 ,  G11C11/40 ,  G11C11/24

CPC classification number: G11C11/412 ,  G11C11/4023 ,  H01L27/108 ,  H03K3/35606 ,  H03K3/356086

Abstract: An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (S) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K).

Abstract translation: 提供具有位线（12），字线（14）和单元电压供应（26）的集成电路存储单元（10）。 集成电路存储单元（10）包括第一时钟线（34）和第二时钟线（36）。 第一晶体管（20）互连到位线（12）和字线（14），用于提供对存储单元（10）的访问。 第二晶体管（22）与电池电压源（26）和第一晶体管（20）互连，由此限定第一节点（S）。 第二晶体管（22）提供从单电池电压源（26）到第一节点（S）的充电路径。 提供电容器（30）并将第一时钟线（34）和第二晶体管（22）互连。 电容器（30）和第二晶体管（22）之间的互连限定第二节点（K）。 电容器（30）在第一时钟线（34）和第二节点（K）之间提供耦合路径，用于从第一时钟线（34）向第二节点（K）有条件地提供电压以在第二时钟线 （K）高于电池电压源（26）。 第三晶体管被提供给存储单元（10）并且互连到第一节点（S）和第二节点（K）和第二时钟线（36）。 第三晶体管（24）在第二时钟线（36）和第二节点（K）之间提供充电路径，用于有条件地维持第二节点（K）的电压。

公开(公告)号：US4940910A

公开(公告)日：1990-07-10

申请号：US360511

申请日：1989-06-02

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4654829A

公开(公告)日：1987-03-31

申请号：US682701

申请日：1984-12-17

Applicant: Ching-Lin Jiang ,  Robert D. Lee

Inventor： Ching-Lin Jiang ,  Robert D. Lee

IPC: G11C5/00 ,  G11C5/14 ,  G11C7/24 ,  G11C13/00

CPC classification number: G11C5/141 ,  G11C5/00 ,  G11C7/24

Abstract: A portable, non-volatile read/write memory module includes a battery for providing standby power that is coupled to a monolithic integrated circuit. Five terminals of the module are removably connected to a host electronic system for transfer of data to and from the module. One of the terminals is a chip enable input that may optionally be used for providing operating power to the monolithic integrated circuit. The monolithic integrated circuit further includes control circuitry that may optionally be coded for providing a security feature for access to data stored in the memory module.

Abstract translation: 便携式非易失性读/写存储器模块包括用于提供耦合到单片集成电路的待机功率的电池。 模块的五个端子可拆卸地连接到主机电子系统，用于将数据传送到模块和从模块传输数据。 其中一个端子是芯片使能输入，其可以可选地用于向单片集成电路提供工作电源。 单片集成电路还包括控制电路，其可选地被编码以提供用于访问存储在存储器模块中的数据的安全特征。

公开(公告)号：US4535427A

公开(公告)日：1985-08-13

申请号：US447348

申请日：1982-12-06

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F5/10 ,  G11C8/04 ,  G11C11/40

CPC classification number: G06F5/10 ,  G11C8/04

Abstract: A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.

Abstract translation: FIFO存储器芯片包括X和Y移位寄存器的形式的读指针和Y指针，Y移位寄存器携带指向矩形单元阵列中的存储单元的一对指针位。