Abstract:
Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Abstract:
SQUIDs may detect local magnetic fields. SQUIDS of varying sizes, and hence sensitivities may detect different magnitudes of magnetic fields. SQUIDs may be oriented to detect magnetic fields in a variety of orientations, for example along an orthogonal reference frame of a chip or wafer. The SQUIDS may be formed or carried on the same chip or wafer as a superconducting processor (e.g., a superconducting quantum processor). Measurement of magnetic fields may permit compensation, for example allowing tuning of a compensation field via a compensation coil and/or a heater to warm select portions of a system. A SQIF may be implemented as a SQUID employing an unconventional grating structure. Successful fabrication of an operable SQIF may be facilitated by incorporating multiple Josephson junctions in series in each arm of the unconventional grating structure.
Abstract:
A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
Abstract:
Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Abstract:
Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.
Abstract:
Methods for reducing errors in calibrated devices comprise detecting outliers, self-checking consistency of measurements, tuning device controls to target values, and absolutely calibrating devices via a first standard and cross-checking the results via a second standard. The first standard may be a calibrated current and the second calibration standard may be a calibrated frequency. A calibrated frequency may be a microwave signal applied to the body of a qubit. Qubit annealing controls can quickly lower and raise the tunnel barrier to measures the oscillation frequency of the qubit between two potential wells.
Abstract:
Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
Abstract:
Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
Abstract:
Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
Abstract:
Methods for reducing errors in calibrated devices comprise detecting outliers, self-checking consistency of measurements, tuning device controls to target values, and absolutely calibrating devices via a first standard and cross-checking the results via a second standard. The first standard may be a calibrated current and the second calibration standard may be a calibrated frequency. A calibrated frequency may be a microwave signal applied to the body of a qubit. Qubit annealing controls can quickly lower and raise the tunnel barrier to measures the oscillation frequency of the qubit between two potential wells.