公开(公告)号：US09071481B2

公开(公告)日：2015-06-30

申请号：US14342367

申请日：2012-08-10

申请人： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

发明人： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

IPC分类号： H04L25/03 ,  H04B1/12

CPC分类号： H04L25/03057 ,  H04B1/123 ,  H04L25/03063 ,  H04L25/03885

摘要： A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

摘要翻译： 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。

公开(公告)号：US08605823B2

公开(公告)日：2013-12-10

申请号：US12679764

申请日：2008-04-29

申请人： Aliazam Abbasfar ,  Farshid Aryanfar

发明人： Aliazam Abbasfar ,  Farshid Aryanfar

IPC分类号： H03C3/00

CPC分类号： H04L27/22 ,  H04B1/16 ,  H04L27/2014 ,  H04L27/2082

摘要： Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.

公开(公告)号：US08510490B2

公开(公告)日：2013-08-13

申请号：US13378939

申请日：2010-06-14

申请人： Aliazam Abbasfar

发明人： Aliazam Abbasfar

IPC分类号： G06F13/00 ,  H03M7/00

CPC分类号： G06F13/4265

摘要： A data encoding scheme for transmission of data from one circuit to another circuit combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data is transmitted from one circuit to another circuit.

摘要翻译： 用于将数据从一个电路传输到另一个电路的数据编码方案结合了DBI编码和非DBI编码，并且使用数据屏蔽信号来指示所使用的编码的类型。 第一状态下的数据掩码信号表示从一个电路发送到另一个电路的数据将被忽略，第二状态的数据屏蔽信号表示从一个电路发送到另一个电路的数据不是 忽略了 如果数据掩码信号处于第二状态，则数据总线反转编码数据的第一子集，并且数据的第二子集与数据总线反转不同。 这样的编码具有当编码数据从一个电路传输到另一个电路时SSO噪声显着降低的优点。

公开(公告)号：US08407558B2

公开(公告)日：2013-03-26

申请号：US12858923

申请日：2010-08-18

申请人： Aliazam Abbasfar

发明人： Aliazam Abbasfar

IPC分类号： H03M13/00

CPC分类号： G06F11/08 ,  G06F11/0793 ,  G06F11/1004

摘要： Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.

摘要翻译： 描述电路的实施例。 在该电路中，编码器电路将一组N个符号编码为代码空间中的给定码字，其中给定码字包括一组M个符号。 M个驱动器耦合到编码器电路并且耦合到信道中的M个链路，其中给定的驱动器将M个符号集合中的给定符号输出到给定的链路上。 此外，耦合到编码器电路的错误检测电路产生并存储与该M个符号组相关联的错误检测信息，其中错误检测信息便于在通信期间错误的类型的随后概率确定 一组M符号到另一个电路。 此外，接收器电路从另一电路接收反馈信息。 该反馈信息包括关于基于代码空间的特征来检测M个符号集合中的另一种类型的错误的错误信息。 此外，控制逻辑基于反馈信息执行补救动作。

公开(公告)号：US20120206280A1

公开(公告)日：2012-08-16

申请号：US13502474

申请日：2010-10-08

申请人： Aliazam Abbasfar ,  John Wilson

发明人： Aliazam Abbasfar ,  John Wilson

IPC分类号： H03M7/34

CPC分类号： H04L25/4915 ,  G06F13/4072 ,  G06F13/4204 ,  G11C7/1006 ,  H04L25/0272

摘要： A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

摘要翻译： 用于将数据从一个电路传输到另一电路的数据编码方案考虑组合的多个字的汉明权重来确定是否反转要发送的单个字。 多字数据编码方案基于组合的多个字中的总HW执行数据反转来执行DBI编码。 基于每个单词的个体汉明重量的总和，决定反转或不反转每个多个单词。 这种编码的优点在于，当编码数据具有通过宽并行总线从一个电路发送到另一个电路的大量字时，SSO噪声显着降低。

公开(公告)号：US20120139638A1

公开(公告)日：2012-06-07

申请号：US13310609

申请日：2011-12-02

申请人： Kambiz Kaviani ,  Amir Amirkhany ,  Aliazam Abbasfar

发明人： Kambiz Kaviani ,  Amir Amirkhany ,  Aliazam Abbasfar

IPC分类号： H03F3/04

CPC分类号： H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/447 ,  H03F2203/45008 ,  H03F2203/45048 ,  H03F2203/45078 ,  H03F2203/45306 ,  H03F2203/45488 ,  H03F2203/45686 ,  H03G1/0029 ,  H03G1/007

摘要： A receiver includes an amplifier and a transconductance bias circuit. The amplifier gain is largely determined by transconductance and load impedance. The transconductance bias circuit varies the transconductance in inverse proportion to the load impedance to maintain the gain over process, voltage, and temperature. Differential amplifiers can use separate transconductance bias circuits for each amplifier leg, and the bias circuits can be independently controlled to minimize common-mode gain and voltage offsets.

摘要翻译： 接收器包括放大器和跨导偏置电路。 放大器增益主要取决于跨导和负载阻抗。 跨导偏置电路会将跨导与负载阻抗成反比变化，以保持增益超过过程，电压和温度。 差分放大器可以为每个放大器支路使用单独的跨导偏置电路，并且可以独立控制偏置电路以最小化共模增益和电压偏移。

公开(公告)号：US20110127990A1

公开(公告)日：2011-06-02

申请号：US12999495

申请日：2009-06-18

申请人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

发明人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

IPC分类号： G01R23/165

CPC分类号： H04L25/49 ,  H04L25/4915

摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

摘要翻译： 数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。 设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。 可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。 检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

公开(公告)号：US20110018599A1

公开(公告)日：2011-01-27

申请号：US12835500

申请日：2010-07-13

申请人： Aliazam Abbasfar

发明人： Aliazam Abbasfar

IPC分类号： H03L7/06

CPC分类号： H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

摘要： A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

摘要翻译： 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US20100183090A1

公开(公告)日：2010-07-22

申请号：US12532107

申请日：2008-04-22

申请人： Aliazam Abbasfar ,  Abbas Komijani

发明人： Aliazam Abbasfar ,  Abbas Komijani

IPC分类号： H04L25/03 ,  H04L27/00

CPC分类号： H04B7/06 ,  H04L27/2614 ,  H04L27/2628

摘要： Embodiments of a communication circuit are described. This communication circuit includes an input node (212) to receive a set of data symbols and a partitioner (216) coupled to the input node. The partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs of adjacent data symbols having different inter-data-symbol spacings in the set of data symbols. This communication circuit also includes M modulators (218-1, 218-N1) coupled to the partitioner, where the given irregular subgroup of data symbols is coupled to a given modulator in the M modulators. Furthermore, the communication circuit includes M output nodes, where a given output node in the M output nodes is coupled to the given modulator and is to couple to an antenna element in M antenna elements (226).

摘要翻译： 描述通信电路的实施例。 该通信电路包括用于接收一组数据符号的输入节点（212）和耦合到输入节点的分割器（216）。 分割器将数据符号组分成M个不规则的数据符号子组，给定的一个数据符号包括数据符号组中的非连续数据符号。 此外，该给定的不规则数据符号子组包括在该组数据符号中具有不同的数据间符号间隔的至少两对相邻数据符号。 该通信电路还包括耦合到分割器的M个调制器（218-1,218-N1），其中给定的不规则子组数据符号耦合到M个调制器中的给定调制器。 此外，通信电路包括M个输出节点，其中M个输出节点中的给定输出节点耦合到给定的调制器，并且耦合到M个天线元件（226）中的天线元件。

公开(公告)号：US20100128813A1

公开(公告)日：2010-05-27

申请号：US12515390

申请日：2007-11-09

申请人： Aliazam Abbasfar ,  Amir Amirkhany

发明人： Aliazam Abbasfar ,  Amir Amirkhany

IPC分类号： H04L27/00 ,  H04B1/10 ,  H04B15/00

CPC分类号： H04L25/03343 ,  H04L5/0007 ,  H04L5/06 ,  H04L25/03057 ,  H04L27/2637 ,  H04L27/2644 ,  H04L2025/03414 ,  H04L2025/03426 ,  H04L2025/0349

摘要： A data transmission circuit comprises a plurality of data preparation circuits and a combiner. Each data preparation circuit receives a respective data stream and generates a respective sub-channel signal. Each respective data stream has a respective symbol rate and a respective Nyquist bandwidth. The combiner combines the respective sub-channel signals to generate a data transmission signal having an associated bandwidth. The bandwidth associated with the data transmission signal is greater than or equal to the sum of the Nyquist bandwidths for the respective data streams. Each data preparation circuit comprises a programmable linear equalizer that equalizes the respective sub-channel signal across the bandwidth of the data transmission signal.

摘要翻译： 数据传输电路包括多个数据准备电路和组合器。 每个数据准备电路接收相应的数据流并产生相应的子信道信号。 每个相应的数据流具有相应的符号率和相应的奈奎斯特带宽。 组合器组合各个子信道信号以产生具有相关带宽的数据传输信号。 与数据传输信号相关联的带宽大于或等于相应数据流的奈奎斯特带宽的总和。 每个数据准备电路包括一个可编程线性均衡器，用于跨数据传输信号的带宽均衡相应的子信道信号。