公开(公告)号：US5471157A

公开(公告)日：1995-11-28

申请号：US220834

申请日：1994-03-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03K5/1532 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/00 ,  H01L25/00

CPC classification number: G11C8/18 ,  H03K5/1534

Abstract: Circuitry for producing a transition detection signal of adequate and optimized duration is disclosed. A transition detection circuit is associated with each of the input terminals from which transitions are to initiate an operating cycle, such as precharge and equilibration in a memory access cycle. Each transition detection circuit produces, responsive to a logic transition at its associated terminal, a transition detection pulse. Those transition detection circuits which produce only brief transition detection pulses are coupled to a centralized summing circuit. The summing circuit generates the transition detection circuit from the logical combination of the transition detection circuits, and includes a delay circuit to lengthen the brief incoming transition detection pulse to the desired duration. In this way, a single placement of the summing circuit can be used to optimize the transition detection pulse duration for initiation of the operating cycle of the integrated circuit.

Abstract translation: 公开了用于产生足够和优化的持续时间的转换检测信号的电路。 转换检测电路与每个输入端子相关联，从该输入端子的转换将开始操作周期，例如存储器访问周期中的预充电和平衡。 每个转换检测电路响应于其相关终端的逻辑转换产生转换检测脉冲。 仅产生简单转换检测脉冲的那些转换检测电路被耦合到集中求和电路。 求和电路从转换检测电路的逻辑组合产生转换检测电路，并且包括延迟电路，以将短暂的输入转变检测脉冲延长到期望的持续时间。 以这种方式，可以使用求和电路的单个放置来优化用于启动集成电路的操作周期的转换检测脉冲持续时间。

公开(公告)号：US5428311A

公开(公告)日：1995-06-27

申请号：US85580

申请日：1993-06-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03K5/13 ,  H03K19/003 ,  H03K17/284

CPC classification number: H03K5/133 ,  H03K19/00323

Abstract: According to the present invention, integrated circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse element having at least one fuse and a transistor element having at least one transistor are placed in parallel to each other between a voltage supply of a gate of the integrated circuit and a corresponding voltage supply of the integrated circuit. When the fuse element is intact, the fuse element provides a relatively low resistance path from the voltage supply of the gate and the corresponding voltage supply of the integrated circuit. However, upon blowing the fuse element, this low resistance path is no longer available. An increased resistance path through the transistor element must be used, and the integrated circuit is slowed down accordingly. The amount of delay introduced to the delay element is a function of the values of the transistors in the transistor element.

Abstract translation: 根据本发明，集成电路提供了选择性地将延迟引入集成电路的定时的能力，而不需要与现有技术中使用的方法相关联的费用和时间。 至少，具有至少一个熔丝的熔丝元件和具有至少一个晶体管的晶体管元件在集成电路的栅极的电压源和集成电路的相应电压源之间彼此并联放置。 当保险丝元件完好无损时，保险丝元件提供从栅极的电压供应和集成电路的相应电压源提供的相对较低的电阻路径。 然而，在熔断熔丝元件时，这个低电阻路径不再可用。 必须使用通过晶体管元件的增加的电阻路径，并且集成电路相应地减慢。 引入延迟元件的延迟量是晶体管元件中的晶体管的值的函数。

公开(公告)号：US5377143A

公开(公告)日：1994-12-27

申请号：US40916

申请日：1993-03-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/062

Abstract: A memory system comprising a memory array having at least two pairs of data lines, first and second data lines corresponding to columns in the memory array. The memory array also includes two level shifter circuits, a first shifter circuit connected to the first lines and a second level shifter circuit connected to the second data lines, wherein the level shifter circuits produce output signals and may be enabled and disabled. A selection signal is used to selectively enable and disable the level shifter circuits, wherein one pair of data lines may be selected. An amplification circuit is connected to the level shifters for amplifying the output signals from the level shifter circuits, and a logic circuit is used to generate logic output signals in response to the amplified output signals from the amplification circuit.

Abstract translation: 一种存储器系统，包括具有至少两对数据线的存储器阵列，对应于存储器阵列中的列的第一和第二数据线。 存储器阵列还包括两个电平移位器电路，连接到第一线的第一移位器电路和连接到第二数据线的第二电平移位器电路，其中电平移位器电路产生输出信号并且可以被使能和禁止。 选择信号用于选择性地启用和禁用电平移位器电路，其中可以选择一对数据线。 放大电路连接到电平移位器，用于放大来自电平移位器电路的输出信号，并且逻辑电路用于响应于来自放大电路的放大的输出信号产生逻辑输出信号。

公开(公告)号：US5355113A

公开(公告)日：1994-10-11

申请号：US901667

申请日：1992-06-22

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F5/14 ,  G06F5/06 ,  G06F5/10 ,  G11C7/00 ,  G06F7/02

CPC classification number: G06F5/14 ,  G06F5/06

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which together comprise a magnitude comparator, determine if a first bit is less than, equal to, or greater than a second bit, and operate to produce a composite comparator output. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. In addition, control of selected bits, such as the most significant bits (MSBs), of the numbers is included and may be used as necessary to avoid a wrap-around condition.

Abstract translation: 适用于FIFO存储器的差分标志逻辑被修改为在不使用减法器电路的情况下快速生成FIFO标志状态。 一起组成幅度比较器的位比较器确定第一位是否小于，等于或大于第二位，并且操作以产生复合比较器输出。 通过将写入计数的读取计数与期望的FIFO标志值相等的值来抵消减法器功能。 此外，包括数字的选择位（诸如最高有效位（MSB））的控制，并且可以根据需要使用以避免环绕条件。

公开(公告)号：US5337273A

公开(公告)日：1994-08-09

申请号：US100084

申请日：1993-07-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G06F12/0891 ,  G11C11/413 ,  G11C7/18 ,  G11C8/14 ,  Y02B60/1225

Abstract: A static random access memory provides interconnection of local wordlines and bit lines to share charge during bulk write operations. Prior to a bulk write cycle, a bit line for each memory cell is driven to a first voltage level. Subsequently, the bit lines and the local wordlines are interconnected for sharing charge between the bit lines and the local wordlines. Next, the bit lines are disconnected from the local wordlines and the bit lines are driven to a second voltage level while the local wordlines are driven to the first voltage level to address the memory cells. Then the bit lines and local wordlines are reconnected to distribute charge from the local wordlines to the bit lines. Lastly, the bit lines are again disconnected from the local wordlines and driven to the first voltage level preparatory to resuming normal operation.

Abstract translation: 静态随机存取存储器提供本地字线和位线的互连，以在批量写入操作期间共享电荷。 在批量写周期之前，每个存储单元的位线被驱动到第一电压电平。 随后，位线和本地字线被互连以在位线和本地字线之间共享电荷。 接下来，位线与本地字线断开，并且将位线驱动到第二电压电平，同时将本地字线驱动到第一电压电平以寻址存储器单元。 然后重新连接位线和本地字线，以将电荷从本地字线分配到位线。 最后，位线再次与本地字线断开并被驱动到准备恢复正常操作的第一电压电平。

公开(公告)号：US5295104A

公开(公告)日：1994-03-15

申请号：US809735

申请日：1991-12-17

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/10 ,  G11C7/02

CPC classification number: G11C7/1048

Abstract: An integrated circuit, such as a memory, having an internal data bus and circuitry for precharging the same is disclosed. Each data conductor in said data bus is associated with a dummy data conductor, which is driven to a complementary logic state from that of its associated data conductor. During precharge and equilibration at the beginning of a cycle, initiated by an address transition detection or by a clock signal, each data conductor is connected to its dummy data conductor so that the data conductor is precharged to a midlevel by way of charge sharing. Also during precharge and equilibration, the data driver is placed in a high impedance state by the sense amplifier output nodes both going to the same logic level. This midlevel precharge allows for faster switching, and reduced instantaneous current, than obtained for rail-to-rail switching. Self-biasing circuits are connected to each of the data conductors and dummy data conductors, to prevent floating conditions during long precharge and equilibration periods. The output stage receiving the data conductor is preferably disabled during precharge and equilibration, so that the data conductor can be precharged near the trip level of the output stage, without risking output stage oscillations. A termination is also provided for the dummy data conductor, matching the load presented by the output stage to the data conductor, so that the data conductor and its dummy data conductor are at complementary states even during transient conditions.

Abstract translation: 公开了具有内部数据总线和用于对其进行预充电的电路的诸如存储器的集成电路。 所述数据总线中的每个数据导体与虚拟数据导体相关联，所述虚拟数据导体被驱动到与其相关联的数据导体的逻辑状态的互补逻辑状态。 在循环开始期间，通过地址转换检测或时钟信号启动的预充电和平衡期间，每个数据导体连接到其虚拟数据导体，使得数据导体通过电荷共享被预充电到中间级。 此外，在预充电和平衡期间，数据驱动器由感测放大器输出节点置于高阻抗状态，两者都达到相同的逻辑电平。 该中级预充电允许比轨至轨切换获得的更快的开关和减小的瞬时电流。 自偏置电路连接到每个数据导体和虚拟数据导体，以防止在长预充电和平衡周期期间的浮动状态。 接收数据导体的输出级优选在预充电和平衡期间被禁用，使得数据导体可以在输出级的跳闸电平附近被预充电，而不会产生输出级振荡。 还为虚拟数据导体提供终端，使输出级呈现的负载与数据导体相匹配，使得数据导体及其虚拟数据导体即使在瞬态条件下也处于互补状态。

公开(公告)号：US5128897A

公开(公告)日：1992-07-07

申请号：US588577

申请日：1990-09-26

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/14 ,  G11C8/18 ,  G11C11/407 ,  G11C11/41 ,  G11C16/06 ,  G11C17/00

CPC classification number: G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/14 ,  G11C8/18

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

公开(公告)号：US5121346A

公开(公告)日：1992-06-09

申请号：US454408

申请日：1989-12-21

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/00 ,  G01R29/027 ,  G06F5/10 ,  G06F5/12 ,  G06F7/02 ,  H03K5/26

CPC classification number: G06F5/12 ,  G01R29/0273 ,  G06F7/026 ,  G06F2205/126

Abstract: In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO. Specific flag values are user-programmed and are stored electronically as binary numbers in registers. The connection between individual subtractor circuits and individual comparator circuits for making the comparison is performed by a program select decoder which utilizes the difference output of the subtractor circuit and the flag program value.

公开(公告)号：US5099148A

公开(公告)日：1992-03-24

申请号：US601288

申请日：1990-10-22

Applicant: David C. McClure ,  James Brady

Inventor： David C. McClure ,  James Brady

IPC: H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K17/16

Abstract: An output driver arrangement for an integrated circuit having multiple output terminals is disclosed. Each of the output drivers is a push-pull driver, with the gates of the pull-up and pull-down transistors each controlled by a logic circuit; the logic circuits perform a logical combination of the data to be presented and an output disable signal. In order to control the switching speed of the outputs, and thus to reduce induced noise, each of the logic circuits share a resistor network at their bias nodes. For example, each of the logic circuits controlling the pull-up device share a resistor network for bias from V.sub.cc, and a resistor network for bias to ground; similarly, each of the logic circuits controlling the pull-down device share a resistor network for bias from V.sub.cc and a resistor network for bias to ground. Various arrangements including fuses may be used to allow selection of the resistance value of each of the networks, according to the performance of the circuit or in response to product demand.

Abstract translation: 公开了一种具有多个输出端的集成电路的输出驱动器装置。 每个输出驱动器都是一个推挽式驱动器，其上拉和下拉晶体管的栅极均由逻辑电路控制; 逻辑电路执行要呈现的数据和输出禁止信号的逻辑组合。 为了控制输出的开关速度，并且因此减小感应噪声，每个逻辑电路在其偏置节点处共享电阻器网络。 例如，控制上拉装置的每个逻辑电路共享用于Vcc偏置的电阻网络和用于偏置到地的电阻网络; 类似地，控制下拉装置的每个逻辑电路共享用于来自Vcc的偏置的电阻网络和用于偏置到地的电阻网络。 可以使用包括保险丝的各种布置来根据电路的性能或响应于产品需求来选择每个网络的电阻值。

公开(公告)号：US4974241A

公开(公告)日：1990-11-27

申请号：US332290

申请日：1989-03-31

Applicant: David C. McClure ,  Mark A. Lysinger

Inventor： David C. McClure ,  Mark A. Lysinger

IPC: G06F1/12 ,  G06F5/12 ,  G11C7/00 ,  H04J3/06 ,  H04L7/00

CPC classification number: H04J3/0626

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.