公开(公告)号：US5598109A

公开(公告)日：1997-01-28

申请号：US626513

申请日：1996-04-02

申请人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

发明人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17744

摘要： A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.

摘要翻译： 提供了可编程逻辑阵列器件，其中可编程逻辑区域以四个成组排列。 该装置包括用于在四个区域的一组内以及某些相邻的可编程逻辑区域中携带信号的直接连接导体，用于在组内和相邻组之间传送信号的本地导体以及用于承载设备范围信号的全局导体。 提供各种导体之间以及导体和可编程逻辑区之间的连接，以尽可能避免开关导体路径来优化连接资源。

公开(公告)号：US06836151B1

公开(公告)日：2004-12-28

申请号：US10781334

申请日：2004-02-17

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K190195

CPC分类号： H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。

公开(公告)号：US06714050B2

公开(公告)日：2004-03-30

申请号：US09898183

申请日：2001-07-03

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K190195

CPC分类号： H03K19/17744 ,  H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

公开(公告)号：US5705939A

公开(公告)日：1998-01-06

申请号：US730351

申请日：1996-10-15

申请人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

发明人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

摘要翻译： 可编程逻辑阵列集成电路器件具有以可交叉行和列的二维阵列布置在器件上的块分组的可编程逻辑区域。 每个块包括相对较少数量的逻辑区域，以减小块中所需的局部反馈电路的尺寸和复杂度。 互连导体沿着块的每一行和一列延伸。 这些导体中的一些沿其长度被分段以允许独立使用每个段。 然而，当需要更长的互连时，相邻的段可以通过段之间的可编程双向开关互连。

公开(公告)号：US5537057A

公开(公告)日：1996-07-16

申请号：US388300

申请日：1995-02-14

申请人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

发明人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17744

摘要： A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.

摘要翻译： 提供了可编程逻辑阵列器件，其中可编程逻辑区域以四个成组排列。 该装置包括用于在四个区域的一组内以及某些相邻的可编程逻辑区域中携带信号的直接连接导体，用于在组内和相邻组之间传送信号的本地导体以及用于承载设备范围信号的全局导体。 提供各种导体之间以及导体和可编程逻辑区之间的连接，以尽可能避免开关导体路径来优化连接资源。

公开(公告)号：US5268598A

公开(公告)日：1993-12-07

申请号：US043146

申请日：1993-03-31

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03R19/177

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

公开(公告)号：US07034570B2

公开(公告)日：2006-04-25

申请号：US11004664

申请日：2004-12-03

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K19/177

CPC分类号： H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。

公开(公告)号：US06278291B1

公开(公告)日：2001-08-21

申请号：US09620922

申请日：2000-07-21

申请人： Cameron McClintock ,  William Leong ,  Richard G. Cliff ,  Bahram Ahanin

发明人： Cameron McClintock ,  William Leong ,  Richard G. Cliff ,  Bahram Ahanin

IPC分类号： H01L2507

CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17796

摘要： A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.

摘要翻译： 可编程逻辑阵列器件具有用于在逻辑区域之间传送信号的多个逻辑区域和导体。 提供几种不同长度的导体，使得逻辑区域之间的大多数连接可以使用接近所需长度的导体而不是浪费地比该长度长得多。

公开(公告)号：US5900743A

公开(公告)日：1999-05-04

申请号：US931251

申请日：1997-09-16

申请人： Cameron McClintock ,  William Leong ,  Richard G. Cliff ,  Bahram Ahanin

发明人： Cameron McClintock ,  William Leong ,  Richard G. Cliff ,  Bahram Ahanin

IPC分类号： H01L25/07 ,  H03K19/04 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796 ,  H03K19/04

摘要： A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.

公开(公告)号：US5828229A

公开(公告)日：1998-10-27

申请号：US847004

申请日：1997-05-01

申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。