公开(公告)号：US07317769B2

公开(公告)日：2008-01-08

申请号：US10418009

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03D1/00

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

公开(公告)号：US10009035B1

公开(公告)日：2018-06-26

申请号：US15495572

申请日：2017-04-24

Applicant: Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

Inventor： Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

IPC: H03M1/06 ,  H03M1/08 ,  H04B1/38 ,  H03M1/12 ,  H04L25/06 ,  H03M1/00

CPC classification number: H04B1/38 ,  H03M1/00 ,  H03M1/007 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/46 ,  H04L25/067

Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

公开(公告)号：US07664170B2

公开(公告)日：2010-02-16

申请号：US10417990

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03H7/30

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  H04J3/04 ,  H04L1/205 ,  H04L25/03343 ,  H04L25/03885

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路包括AGC环路，均衡器和均衡器反馈环路。 AGC环路包括增益路径和耦合到均衡器的输出的反馈路径。 均衡器反馈环路耦合到均衡器的输出，并产生频谱整形控制设置，均衡器用于在均衡器输出端产生均衡的高速串行比特流。

公开(公告)号：US20090304054A1

公开(公告)日：2009-12-10

申请号：US12132923

申请日：2008-06-04

Applicant: Davide Tonietto ,  John Hogeboom

Inventor： Davide Tonietto ,  John Hogeboom

IPC: H04B1/38

CPC classification number: H04L25/03343 ,  H04L1/205 ,  H04L1/243 ,  H04L2025/03356

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract translation: 第一设备通过通信链路的第一分支向第二设备发送数据。 该第二设备将所接收的数据模式循环通过通信链路的第二分支。 确定环回数据模式的误码率，并响应于此来调整应用于发送数据模式的预加重。 第一设备进一步扰乱数据模式通信信号，以增加误码率。 调整预加重，以便在存在扰动的情况下减少确定的循环数据模式中的误码率。 迭代地执行用于干扰信号和调整预加重的步骤，随着每个迭代的信号的扰动增加，并且每次迭代改进预加重的调整。 该信号通过将调制抖动注入到信号（增加每次迭代）并调整信号的幅度（每次迭代减少）来扰乱。

公开(公告)号：US20080107424A1

公开(公告)日：2008-05-08

申请号：US11970191

申请日：2008-01-07

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04B10/00

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

公开(公告)号：US07206337B2

公开(公告)日：2007-04-17

申请号：US10393613

申请日：2003-03-21

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04L5/16

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a clock and data recovery circuit and an output pre-emphasis circuit. The output pre-emphasis circuit controllably modifies the spectrum of the high-speed bit stream to pre-compensate for the spectral characteristics of a signal path upon which the high-speed bit stream will be output. In the RX path, pre-compensation is performed based upon the properties of the PCB and a servicing connector. In the TX path, pre-compensation is performed based upon the properties of a line side connector and a line side media.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括时钟和数据恢复电路以及输出预加重电路。 输出预加重电路可控制地修改高速比特流的频谱以对要输出高速比特流的信号路径的频谱特性进行预补偿。 在RX路径中，基于PCB的属性和维修连接器进行预补偿。 在TX路径中，基于线路侧连接器和线路侧介质的特性进行预补偿。

公开(公告)号：US06320458B1

公开(公告)日：2001-11-20

申请号：US09567789

申请日：2000-05-09

Applicant: Paolo Cusinato ,  Gabriele Gandolfi ,  Vittorio Colonna ,  Davide Tonietto

Inventor： Paolo Cusinato ,  Gabriele Gandolfi ,  Vittorio Colonna ,  Davide Tonietto

IPC: G05F302

CPC classification number: H03L7/06 ,  G05F3/24 ,  H03L7/0995

Abstract: An integrated circuit has a first external supply terminal and a second external supply terminal for applying an external supply voltage to the circuit. The integrated circuit includes an analog unit supplied by at least one internal supply voltage derived from the external supply voltage, a low-pass filter connected to the first external supply terminal and to the second external supply terminal, and a driver connected between the low-pass filter and the analog unit for supplying the at least one internal supply voltage.

Abstract translation: 集成电路具有用于向电路施加外部电源电压的第一外部电源端子和第二外部电源端子。 集成电路包括由外部电源电压导出的至少一个内部电源电压提供的模拟单元，连接到第一外部电源端子和第二外部电源端子的低通滤波器， 通过滤波器和用于提供至少一个内部电源电压的模拟单元。

公开(公告)号：US10153917B1

公开(公告)日：2018-12-11

申请号：US15656938

申请日：2017-07-21

Applicant: Davide Tonietto ,  Dustin Tarl Dunwell ,  Anthony Chan Carusone

Inventor： Davide Tonietto ,  Dustin Tarl Dunwell ,  Anthony Chan Carusone

IPC: H04L12/40 ,  H04L25/03 ,  H04L7/00

Abstract: Methods, integrated circuits and computer-readable media for communicating back-channel data over a data link by modulating the phase or frequency of a clock signal of a data signal transmitted over the data link. Slow modulation of the clock signal allows it to be detected and extracted by a receiver without affecting the integrity or bit rate of the data signal. Some embodiments allow the functionality to be implemented without the use of extra hardware in the transmitter or receiver or either.

公开(公告)号：US20100246658A1

公开(公告)日：2010-09-30

申请号：US12795808

申请日：2010-06-08

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04B1/10

CPC classification number: H04B10/291

Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.

Abstract translation: 公开了一种用于优化收发器设备的操作的系统和方法。 该方法可以包括通过具有第一频率响应的第一路径和具有第二频率响应的第二路径并行处理输入信号。 第二频率响应可能高于第一频率响应。 可以组合来自第一和第二路径的信号，产生具有所需增益和频率的输出信号。 并行处理可以调整第一路径和第二路径中的至少一个的增益。 并行处理可以均衡第一频率响应和第二频率响应中的至少一个。 输入信号可以来自10GBit以太网信道和/或光纤信道。

公开(公告)号：US20090190649A1

公开(公告)日：2009-07-30

申请号：US12419100

申请日：2009-04-06

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03K5/159

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质的介质耦合器，例如铜介质或光学介质。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调整TX信号，并向板侧接口提供TX信号。