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公开(公告)号：US20050218985A1
公开(公告)日：2005-10-06
申请号：US10813941
申请日：2004-03-30
Applicant: Semyon Lebedev , Eshel Gordon
Inventor： Semyon Lebedev , Eshel Gordon
CPC classification number: H03F3/45192 , H03F1/305 , H03F3/45654 , H03F2203/45028 , H03F2203/45418 , H03F2203/45666
Abstract: A fully differential amplifier having a start-up circuit is described. The fully differential amplifier may be a two-stage amplifier with a start-up circuit coupled between the stages. The start-up circuit may include a sense circuit coupled between a common mode input and internal nodes that are connect to output transistors of the fully differential amplifier. The sense circuit produces a reset signal that forces the fully differential amplifier into a mode of operation.
Abstract translation: 描述具有启动电路的全差分放大器。 全差分放大器可以是两级放大器，其中启动电路耦合在各级之间。 启动电路可以包括耦合在共模输入和连接到全差分放大器的输出晶体管的内部节点之间的感测电路。 感测电路产生复位信号，迫使全差分放大器进入工作模式。
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公开(公告)号：US10009035B1
公开(公告)日：2018-06-26
申请号：US15495572
申请日：2017-04-24
Applicant: Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
Inventor： Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
CPC classification number: H04B1/38 , H03M1/00 , H03M1/007 , H03M1/12 , H03M1/1215 , H03M1/46 , H04L25/067
Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.
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公开(公告)号：US20130082853A1
公开(公告)日：2013-04-04
申请号：US13251935
申请日：2011-10-03
Applicant: Khurram MUHAMMAD , Tajinder Manku , Semyon Lebedev
Inventor： Khurram MUHAMMAD , Tajinder Manku , Semyon Lebedev
Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.
Abstract translation: 公开了一种数模转换器。 该转换器包括梯度校正模块，该梯度校正模块基于梯度误差的模型产生校正项。 然后将校正项应用于数字域中的信号路径或应用于模拟域中的数模转换器的输出。 用于产生校正项的模型基于当前源元素阵列中的垂直梯度误差，其可以使用二阶多项式来建模和校准。 此外，公开了具有奈奎斯特DAC和过采样DAC的数模转换器。 当使能过采样DAC时，可能会增加奈奎斯特DAC的分辨率，同时降低转换速率。
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Patent Agency Ranking
公开(公告)号：US07129782B2
公开(公告)日：2006-10-31
申请号：US10813941
申请日：2004-03-30
Applicant: Semyon Lebedev , Eshel Gordon
Inventor： Semyon Lebedev , Eshel Gordon
IPC: H03F3/45
CPC classification number: H03F3/45192 , H03F1/305 , H03F3/45654 , H03F2203/45028 , H03F2203/45418 , H03F2203/45666
Abstract: A fully differential amplifier having a start-up circuit is described. The fully differential amplifier may be a two-stage amplifier with a start-up circuit coupled between the stages. The start-up circuit may include a sense circuit coupled between a common mode input and internal nodes that are connect to output transistors of the fully differential amplifier. The sense circuit produces a reset signal that forces the fully differential amplifier into a mode of operation.
Abstract translation: 描述具有启动电路的全差分放大器。 全差分放大器可以是两级放大器，其中启动电路耦合在各级之间。 启动电路可以包括耦合在共模输入和连接到全差分放大器的输出晶体管的内部节点之间的感测电路。 感测电路产生复位信号，迫使全差分放大器进入工作模式。
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公开(公告)号：US11133812B1
公开(公告)日：2021-09-28
申请号：US17080263
申请日：2020-10-26
Applicant: Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
Inventor： Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
Abstract: Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.
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公开(公告)号：US08581760B2
公开(公告)日：2013-11-12
申请号：US13251935
申请日：2011-10-03
Applicant: Khurram Muhammad , Tajinder Manku , Semyon Lebedev
Inventor： Khurram Muhammad , Tajinder Manku , Semyon Lebedev
IPC: H03M1/12
Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.
Abstract translation: 公开了一种数模转换器。 该转换器包括梯度校正模块，该梯度校正模块基于梯度误差的模型产生校正项。 然后将校正项应用于数字域中的信号路径或应用于模拟域中的数模转换器的输出。 用于产生校正项的模型基于当前源元素阵列中的垂直梯度误差，其可以使用二阶多项式来建模和校准。 此外，公开了具有奈奎斯特DAC和过采样DAC的数模转换器。 当使能过采样DAC时，可能会增加奈奎斯特DAC的分辨率，同时降低转换速率。
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公开(公告)号：US09871529B1
公开(公告)日：2018-01-16
申请号：US15425653
申请日：2017-02-06
Applicant: Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
Inventor： Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
Abstract: Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.
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公开(公告)号：US06741200B2
公开(公告)日：2004-05-25
申请号：US10218041
申请日：2002-08-14
Applicant: Semyon Lebedev
Inventor： Semyon Lebedev
IPC: H03M138
CPC classification number: H03M1/1023 , G11C27/026 , H03M1/0682 , H03M1/38
Abstract: Briefly, a stage amplifier comprises a differential amplifier having stages and a switch to connect a first differential output of a stage with a second differential output of the stage at a beginning of a conversion cycle.
Abstract translation: 简言之，舞台放大器包括具有级的差分放大器和用于在转换周期开始时将级的第一差分输出与级的第二差分输出连接的开关。
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