公开(公告)号：US06607001B1

公开(公告)日：2003-08-19

申请号：US09427789

申请日：1999-10-27

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B304

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.

公开(公告)号：US06601595B2

公开(公告)日：2003-08-05

申请号：US10231730

申请日：2002-08-28

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B304

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.

Abstract translation: 本发明涉及一种在改进的常规气体蚀刻/漂洗或干燥容器中清洗和干燥半导体结构的方法。

公开(公告)号：US08454760B2

公开(公告)日：2013-06-04

申请号：US12476139

申请日：2009-06-01

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/02

CPC classification number: H01L21/02057 ,  H01L21/67051 ,  H01L21/67057

Abstract: Several methods of removing contaminant particles from a surface of a substrate are disclosed herein. In one embodiment, the method includes directing an incompressible fluid spray onto a surface of a substrate to remove contaminant particles from the surface. In an embodiment, the surface of the substrate and the nozzle are both immersed in an incompressible fluid. The fluid can flow across the surface of the substrate to remove the contaminant particles from the area. The fluid spray can be positioned normal to the substrate surface, or can be positioned at an angle relative to the substrate surface.

Abstract translation: 本文公开了从衬底的表面去除污染物颗粒的几种方法。 在一个实施例中，该方法包括将不可压缩的流体喷雾引导到基底的表面上以从表面去除污染物颗粒。 在一个实施例中，基板和喷嘴的表面都浸没在不可压缩流体中。 流体可以流过基板的表面以从该区域去除污染物颗粒。 流体喷雾可以垂直于基底表面定位，或者可以相对于基底表面成一定角度定位。

公开(公告)号：US07468534B2

公开(公告)日：2008-12-23

申请号：US11216417

申请日：2005-08-30

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27/108

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US20080290432A1

公开(公告)日：2008-11-27

申请号：US12153073

申请日：2008-05-13

Applicant: Donald L. Yates ,  Joel A. Drewes

Inventor： Donald L. Yates ,  Joel A. Drewes

IPC: H01L29/82

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L21/7684

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract translation: 本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层 在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

公开(公告)号：US07307306B2

公开(公告)日：2007-12-11

申请号：US11426768

申请日：2006-06-27

Applicant: Donald L. Yates ,  Karen T Signorini

Inventor： Donald L. Yates ,  Karen T Signorini

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L27/222 ,  H01L21/32139 ,  H01L43/12

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract translation: 描述了一种用于形成MRAM位的方法，其包括在集成电路结构上提供覆盖层。 在一个实施例中，覆盖层包括钽。 第一掩模层形成在覆盖层之后，随后是第二掩模层。 第一掩模层和第二掩模层可以通过相同的蚀刻工艺进行蚀刻。 蚀刻第一和第二掩模层。 蚀刻残渣从第一和第二掩模层去除。 然后选择性地去除第一掩模层，并且残留第二掩模层。

公开(公告)号：US07285811B2

公开(公告)日：2007-10-23

申请号：US11513244

申请日：2006-08-31

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L29/76 ,  H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract translation: 本发明提供一种在制造期间使电短路发生最小化的MRAM电池。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元的厚度的厚度。 图案化和蚀刻第一介电层以在单元形状的第一导体上形成开口。 包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

公开(公告)号：US07132299B2

公开(公告)日：2006-11-07

申请号：US10789381

申请日：2004-02-27

Applicant: Donald L. Yates ,  Karen T Signorini

Inventor： Donald L. Yates ,  Karen T Signorini

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L21/32139 ,  H01L43/12

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract translation: 描述了一种用于形成MRAM位的方法，其包括在集成电路结构上提供覆盖层。 在一个实施例中，覆盖层包括钽。 第一掩模层形成在覆盖层之后，随后是第二掩模层。 第一掩模层和第二掩模层可以通过相同的蚀刻工艺进行蚀刻。 蚀刻第一和第二掩模层。 蚀刻残渣从第一和第二掩模层去除。 然后选择性地去除第一掩模层，并且残留第二掩模层。

公开(公告)号：US06896740B2

公开(公告)日：2005-05-24

申请号：US10027951

申请日：2001-12-19

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  B08B7/04 ,  B08B7/00

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an embodiment of the present invention, a semiconductor structure is placed into a first treatment vessel and chemically treated. Following the chemical treatment, the semiconductor structure is transferred directly to a second treatment vessel where it is rinsed with DI water and then dried. The second treatment vessel is flooded with both DI water and a gas that is inert to the ambient, such as nitrogen, to form a DI water bath upon which an inert atmosphere is maintained during rinsing. Next, an inert gas carrier laden with IPA vapor is fed into the second treatment vessel. After sufficient time, a layer of IPA has formed upon the surface of the DI water bath to form an IPA-DI water interface. The semiconductor structure is drawn out of the DI water bath at a rate that allows substantially all DI water, and contaminants therein, to be entrained beneath the IPA-DI water interface.

Abstract translation: 本发明涉及一种在改进的常规气体蚀刻/漂洗或干燥容器中清洗和干燥半导体结构的方法。 在本发明的一个实施例中，将半导体结构放置在第一处理容器中并进行化学处理。 化学处理后，将半导体结构直接转移到第二处理容器，在其中用DI水冲洗然后干燥。 第二处理容器充满了DI水和对环境如氮气是惰性的气体，以形成在洗涤期间保持惰性气氛的去离子水浴。 接下来，将载有IPA蒸气的惰性气体载体进料到第二处理容器中。 在足够的时间之后，在去离子水浴表面上形成一层IPA以形成IPA-DI水界面。 将半导体结构从DI水浴中抽出，其速率允许基本上所有去离子水和其中的污染物被夹带在IPA-DI水界面下面。

公开(公告)号：US06864186B1

公开(公告)日：2005-03-08

申请号：US09123430

申请日：1998-07-28

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/04 ,  H01L21/00 ,  H01L21/3213 ,  H01L21/302 ,  B08B6/00

CPC classification number: H01L21/67086 ,  B08B3/048 ,  H01L21/32134

Abstract: A method and apparatus for reducing the contaminants in a wet etching bath by rapidly removing a substantial portion of the etching liquid from the bath such that the contaminants are removed from the air/liquid interface of the bath surface is described. By rapidly removing a substantial portion of the etching liquid from the bath, contaminants that are trapped by eddy currents and liquid/air surface tension forces are greatly reduced at the surface of the bath. The semiconductor wafers treated showed reduced levels of contamination.

Abstract translation: 描述了通过从浴中快速去除蚀刻液的大部分从而从浴表面的空气/液体界面去除污染物来减少湿蚀刻槽中的污染物的方法和装置。 通过从浴中快速去除蚀刻液体的主要部分，在浴表面大大减少了被涡流捕获的污染物和液/空气表面张力。 处理的半导体晶片显示出降低的污染水平。