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21.发明申请Integrated Circuit Having Gates and Active Regions Forming a Regular Grating 失效具有栅格和有源区域的集成电路形成常规光栅公开(公告)号：US20080210981A1
公开(公告)日：2008-09-04
申请号：US12120878
申请日：2008-05-15
申请人： Leland Chang , Hon-Sum Philip Wong
发明人： Leland Chang , Hon-Sum Philip Wong
IPC分类号： H01L29/80
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.
摘要翻译： 半导体器件包括可连接到一个或多个导体的多个可重复的电路单元，至少提供与电路单元的电连接和/或单元中的一个或多个电路元件之间的电连接。 每个电路单元被配置成具有栅极和形成光栅的有源区，其中，对于器件中的给定有源层，每个有源区的宽度相对于彼此基本相同，任何两个相邻的有源区之间的间隔 基本上相同，每个栅极的宽度相对于彼此基本相同，并且任何两个相邻栅极之间的间隔基本相同。
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22.发明授权公开(公告)号：US07402848B2
公开(公告)日：2008-07-22
申请号：US11761741
申请日：2007-06-12
申请人： Leland Chang , Hon-Sum Philip Wong
发明人： Leland Chang , Hon-Sum Philip Wong
IPC分类号： H01L29/80
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.
摘要翻译： 半导体器件包括可连接到一个或多个导体的多个可重复的电路单元，至少提供与电路单元的电连接和/或单元中的一个或多个电路元件之间的电连接。 每个电路单元被配置成具有栅极和形成光栅的有源区，其中，对于器件中的给定有源层，每个有源区的宽度相对于彼此基本相同，任何两个相邻的有源区之间的间隔 基本上相同，每个栅极的宽度相对于彼此基本相同，并且任何两个相邻栅极之间的间隔基本相同。
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公开(公告)号：US07385251B2
公开(公告)日：2008-06-10
申请号：US11334170
申请日：2006-01-18
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.
摘要翻译： 区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近半导体层的上表面的半导体层中的第二导电类型的有源区，以及至少一个沟槽电极，该沟槽电极基本垂直延伸穿过活性层 并且至少部分地进入半导体层。 门控二极管的第一端子电连接到沟槽电极，并且至少第二端子电连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一模式和第二模式中的一个工作。 第一模式的特征在于在基本上围绕沟槽电极的半导体层中产生反型层。 门控二极管具有第一模式中的第一电容和第二模式中的第二电容，第一电容基本上大于第二电容。
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公开(公告)号：US20060255850A1
公开(公告)日：2006-11-16
申请号：US11491701
申请日：2006-07-24
申请人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
发明人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
IPC分类号： H03K3/356
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。
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公开(公告)号：US20060146638A1
公开(公告)日：2006-07-06
申请号：US11069018
申请日：2005-02-28
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译： 用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。 写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。 读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。 读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。 存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。 存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。
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公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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27.发明授权Slab inductor device providing efficient on-chip supply voltage conversion and regulation 有权板式电感器件提供有效的片上电源电压转换和调节公开(公告)号：US09124173B2
公开(公告)日：2015-09-01
申请号：US13589280
申请日：2012-08-20
申请人： Leland Chang , David Goren , Naigang Wang
发明人： Leland Chang , David Goren , Naigang Wang
摘要： A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.
摘要翻译： 诸如降压调节器电路的电压转换电路具有耦合到电压源的多个开关; 具有长度，宽度和厚度的板式电感器，其中所述扁平电感器耦合在所述多个开关之间，并且在所述多个开关的操作期间负载并承载负载电流。 电压转换电路还可以包括用于减少或消除导致回流的同一芯片（例如电网）上的其它导线的有害影响并由此降低该扁平电感器的功能性的装置。 在一个实施例中，电线可以进一步远离板式电感器，并且在另一个实施例中，磁性材料可用于屏蔽平板电感器与至少一个这样的干扰导体。
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公开(公告)号：US08878298B2
公开(公告)日：2014-11-04
申请号：US13346165
申请日：2012-01-09
CPC分类号： H01L29/7856 , H01L29/66795
摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。
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公开(公告)号：US08604832B1
公开(公告)日：2013-12-10
申请号：US13524562
申请日：2012-06-15
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/00
CPC分类号： H03K19/0963 , H03K19/096
摘要： A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.
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公开(公告)号：US20130260525A1
公开(公告)日：2013-10-03
申请号：US13438437
申请日：2012-04-03
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.
摘要翻译： 一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的 栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。
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