-
公开(公告)号：US07385251B2
公开(公告)日：2008-06-10
申请号：US11334170
申请日：2006-01-18
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.
摘要翻译： 区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近半导体层的上表面的半导体层中的第二导电类型的有源区，以及至少一个沟槽电极，该沟槽电极基本垂直延伸穿过活性层 并且至少部分地进入半导体层。 门控二极管的第一端子电连接到沟槽电极，并且至少第二端子电连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一模式和第二模式中的一个工作。 第一模式的特征在于在基本上围绕沟槽电极的半导体层中产生反型层。 门控二极管具有第一模式中的第一电容和第二模式中的第二电容，第一电容基本上大于第二电容。
-
公开(公告)号：US07884411B2
公开(公告)日：2011-02-08
申请号：US12051116
申请日：2008-03-19
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L27/01 , H01L27/12
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.
摘要翻译： 区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近其上表面的半导体层中的第二导电类型的有源区，以及至少一个垂直延伸穿过有源区的沟槽电极，并且至少 部分地进入半导体层。 栅极二极管的第一端子连接到沟槽电极，并且第二端子连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一和第二模式中的一个工作。 第一模式的特征在于在围绕沟槽电极的半导体层中产生反型层。 门控二极管在第一模式中具有第一电容，在第二模式中具有第二电容，第一电容大于第二电容。
-
公开(公告)号：US20080164507A1
公开(公告)日：2008-07-10
申请号：US12051116
申请日：2008-03-19
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/108 , H01L29/93 , H01L21/329
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.
摘要翻译： 区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近其上表面的半导体层中的第二导电类型的有源区，以及至少一个垂直延伸穿过有源区的沟槽电极，并且至少 部分地进入半导体层。 栅极二极管的第一端子连接到沟槽电极，并且第二端子连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一和第二模式中的一个工作。 第一模式的特征在于在围绕沟槽电极的半导体层中产生反型层。 门控二极管在第一模式中具有第一电容，在第二模式中具有第二电容，第一电容大于第二电容。
-
4.发明授权公开(公告)号：US07116594B2
公开(公告)日：2006-10-03
申请号：US10933706
申请日：2004-09-03
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。
-
公开(公告)号：US20110298440A1
公开(公告)日：2011-12-08
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： G05F5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译： 用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域 以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号 以Vdd摆动水平运行。
-
公开(公告)号：US07242629B2
公开(公告)日：2007-07-10
申请号：US11491701
申请日：2006-07-24
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。
-
公开(公告)号：US07106620B2
公开(公告)日：2006-09-12
申请号：US11069018
申请日：2005-02-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译： 用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。 写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。 读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。 读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。 存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。 存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。
-
公开(公告)号：US08629705B2
公开(公告)日：2014-01-14
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： H03L5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译： 用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域 以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号 以Vdd摆动水平运行。
-
9.发明授权Structure and method for adjusting threshold voltage of the array of transistors 有权用于调整晶体管阵列的阈值电压的结构和方法公开(公告)号：US08859302B2
公开(公告)日：2014-10-14
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L21/66 , G11C11/412 , H01L27/11 , H01L27/12 , H01L21/84 , H01L27/115 , H01L29/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译： 一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。 可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。 注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。
-
公开(公告)号：US08735990B2
公开(公告)日：2014-05-27
申请号：US11679869
申请日：2007-02-28
IPC分类号： H01L21/70 , H01L27/085 , H01L29/06
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7851
摘要： The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.
摘要翻译： 本发明的实施例提供了一种用于Rad-hard FinFET或台面的结构和方法。 更具体地，提供了具有至少一个翅片或台面的半导体结构，其包括在隔离区域上的沟道区域。 掺杂衬底区域也设置在鳍片的下方，其中掺杂衬底区域具有与沟道区域的第二极性相反的第一极性。 隔离区域接触掺杂衬底区域。 该结构还包括覆盖沟道区域和隔离区域的至少一部分的栅电极。 栅极电极包括在鳍片的沟道区域下方的下部，其中栅电极的下部包括至少翅片厚度的二分之一的高度。
-
-
-
-
-
-
-
-
-
搜索结果
104 条记录 (耗时 0.029 秒)