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    DRAM signal margin test method
    21.
    发明授权
    DRAM signal margin test method 失效
    DRAM信号余量测试方法

    公开(公告)号：US5610867A

    公开(公告)日：1997-03-11

    申请号：US535446

    申请日：1995-09-28

    Applicant: John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

    Inventor： John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

    IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/50 ,  G11C7/00 ,  G11C29/00

    CPC classification number: G11C11/4091 ,  G11C29/50 ,  G06F2201/81 ,  G11C11/401

    Abstract: In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.

    Abstract translation: 在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。 在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。 控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。 此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。 因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。 因此，数据从感测放大器传递到第二读出放大器和芯片外。 数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。 此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。 代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。 可以选择VS来确定高和低信号余量。

    Corner protected shallow trench isolation device
    22.
    发明授权
    Corner protected shallow trench isolation device 失效
    角保护浅沟隔离装置

    公开(公告)号：US5521422A

    公开(公告)日：1996-05-28

    申请号：US348709

    申请日：1994-12-02

    Applicant: Jack A. Mandelman ,  Brian J. Machesney ,  Hing Wong ,  Michael D. Armacost ,  Pai-Hung Pan

    Inventor： Jack A. Mandelman ,  Brian J. Machesney ,  Hing Wong ,  Michael D. Armacost ,  Pai-Hung Pan

    IPC: H01L21/762 ,  H01L29/00

    CPC classification number: H01L21/76224

    Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

    Abstract translation: 一种用于防止栅包绕和角寄生泄漏的半导体结构，包括具有平坦表面的半导体衬底。 沟槽位于衬底中，沟槽具有侧壁。 沟槽和表面的交点形成一个角落。 介电线路沟槽的侧壁。 并且，与拐角共同对准的拐角电介质在拐角处延伸超过衬底的最小尺寸距离。

    Compositions and methods for treating coagulation related disorders
    26.
    发明申请
    Compositions and methods for treating coagulation related disorders 审中-公开
    用于治疗凝血相关疾病的组合物和方法

    公开(公告)号：US20060159675A1

    公开(公告)日：2006-07-20

    申请号：US11311702

    申请日：2005-12-19

    Applicant: Jin-An Jiao ,  Hing Wong ,  Jack Egan

    Inventor： Jin-An Jiao ,  Hing Wong ,  Jack Egan

    IPC: A61K39/395

    CPC classification number: C07K16/36 ,  A61K2039/505 ,  C07K2317/24 ,  C07K2317/55

    Abstract: Disclosed are methods for preventing or treating sepsis, a sepsis-related condition or an inflammatory disease in a mammal. In one embodiment, the method includes administering to the mammal a therapeutically effective amount of at least one humanized antibody, chimeric antibody, or fragment thereof that binds specifically to tissue factor (TF) to form a complex in which factor X or factor IX binding to the complex is inhibited and the administration is sufficient to prevent or treat the sepsis in the mammal. The invention has a wide spectrum of useful applications including treating sepsis, disorders related to sepsis, and inflammatory diseases such as arthritis.

    Abstract translation: 公开了用于预防或治疗哺乳动物中败血症，败血症相关病症或炎性疾病的方法。 在一个实施方案中，所述方法包括向哺乳动物施用治疗有效量的至少一种特异性结合组织因子（TF）的人源化抗体，嵌合抗体或其片段，以形成其中因子X或因子IX与 复合物被抑制，并且给药足以预防或治疗哺乳动物的败血症。 本发明具有广泛的有用应用，包括治疗败血症，与败血症有关的疾病，以及诸如关节炎的炎性疾病。

    Vaccines, methods, and antibodies specific for lipoteichoic acid of gram positive bacteria
    27.
    发明申请
    Vaccines, methods, and antibodies specific for lipoteichoic acid of gram positive bacteria 失效
    针对革兰氏阳性菌的脂磷壁酸的疫苗，方法和抗体

    公开(公告)号：US20060002939A1

    公开(公告)日：2006-01-05

    申请号：US11193440

    申请日：2005-08-01

    Applicant: Gerald Fischer ,  Richard Schuman ,  Hing Wong ,  Jeffrey Stinson

    Inventor： Gerald Fischer ,  Richard Schuman ,  Hing Wong ,  Jeffrey Stinson

    IPC: A61K39/40

    CPC classification number: C07K14/195 ,  A61K38/00 ,  A61K39/00 ,  A61K2039/505 ,  C07K16/1267 ,  C07K16/1271 ,  C07K2317/24 ,  C07K2317/33 ,  C07K2317/34 ,  C07K2317/73 ,  C07K2317/77 ,  C07K2319/00

    Abstract: The present invention encompasses monoclonal and chimeric antibodies that bind to lipoteichoic acid of Gram positive bacteria. The antibodies also bind to whole bacteria and enhance phagocytosis and killing of the bacteria in vitro and enhance protection from lethal infection in vivo. The mouse monoclonal antibody has been humanized and the resulting chimeric antibody provides a previously unknown means to diagnose, prevent and/or treat infections caused by gram positive bacteria bearing lipoteichoic acid. This invention also encompasses a peptide mimic of the lipoteichoic acid epitope binding site defined by the monoclonal antibody. This epitope or epitope peptide mimic identifies other antibodies that may bind to the lipoteichoic acid epitope. Moreover, the epitope or epitope peptide mimic provides a valuable substrate for the generation of vaccines or other therapeutics.

    Abstract translation: 本发明包括与革兰氏阳性细菌的脂磷壁酸结合的单克隆抗体和嵌合抗体。 抗体还结合全细菌，增强体外吞噬细菌和杀死细菌，增强体内致死感染的保护作用。 小鼠单克隆抗体已经人源化，所得到的嵌合抗体提供了以前未知的用于诊断，预防和/或治疗由具有脂磷壁酸的革兰氏阳性细菌引起的感染的方法。 本发明还包括由单克隆抗体限定的脂磷壁酸结合位点的肽模拟物。 该表位或表位肽模拟物鉴定可结合脂磷壁酸表位的其它抗体。 此外，表位或表位肽模拟物为生成疫苗或其他治疗剂提供了有价值的底物。

    Fabrication of interconnects with two different thicknesses
    29.
    发明授权
    Fabrication of interconnects with two different thicknesses 失效
    制造具有两种不同厚度的互连

    公开(公告)号：US6136686A

    公开(公告)日：2000-10-24

    申请号：US897172

    申请日：1997-07-18

    Applicant: Jeffrey P. Gambino ,  Mark Jaso ,  Hing Wong

    Inventor： Jeffrey P. Gambino ,  Mark Jaso ,  Hing Wong

    IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763

    CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76897 ,  H01L27/10882 ,  H01L27/10894

    Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

    Abstract translation: 通过例如蚀刻停止层或植入来提供层的差分蚀刻允许根据阻挡掩模（其不需要高准确度的配准）来执行第二槽蚀刻，以提供槽或凹槽 不同深度的绝缘子层。 当通过金属沉积填充凹槽或凹槽时，根据镶嵌工艺通过平面化图案化，可以实现和优化不同厚度的结构坚固的导体并且被优化以增强集成电路的不同功能区域中的抗噪声和/或信号传播速度，例如 作为动态随机存取存储器的所谓阵列和支持部分。

    Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device
    30.
    发明授权
    Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device 失效
    用于可修复半导体存储器件中冗余字线替换的方法和装置

    公开(公告)号：US5963489A

    公开(公告)日：1999-10-05

    申请号：US47086

    申请日：1998-03-24

    Applicant: Toshiaki Kirihata ,  John K. DeBrosse ,  Yohji Watanabe ,  Hing Wong

    Inventor： Toshiaki Kirihata ,  John K. DeBrosse ,  Yohji Watanabe ,  Hing Wong

    IPC: G11C29/04 ,  G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/806 ,  G11C29/848

    Abstract: A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.

    Abstract translation: 一种用于修复半导体存储器件的方法和装置。 提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第 正常补码字线。 地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。 冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。 这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

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