公开(公告)号：US20110010484A1

公开(公告)日：2011-01-13

申请号：US12499219

申请日：2009-07-08

申请人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

发明人： Steven Sprouse ,  Jianmin Huang ,  Chris Avila ,  Yichao Huang ,  Emilio Yero

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C11/5628 ,  G11C2211/5648

摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

摘要翻译： 在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。 对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。 由于发生更大程度的并行处理，记录单元的整体编程时间减少。 当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。 编程完成后，存储器信号通知主机传送下一个记录单元。 数据页可以包括下页，中页和上页。

公开(公告)号：US20090262578A1

公开(公告)日：2009-10-22

申请号：US12495200

申请日：2009-06-30

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US07467253B2

公开(公告)日：2008-12-16

申请号：US11404454

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US20070245067A1

公开(公告)日：2007-10-18

申请号：US11404454

申请日：2006-04-13

申请人： Emilio Yero

发明人： Emilio Yero

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

摘要翻译： 热计数记录块所经历的擦除操作的数量。 热计数存储在块的开销数据区域中，并且通过位于与块相同的衬底上的电路来更新。 在存储器具有两个或更多个平面的情况下，每个平面具有用于更新热计数的电路。

公开(公告)号：US07206230B2

公开(公告)日：2007-04-17

申请号：US11097590

申请日：2005-04-01

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US20060221704A1

公开(公告)日：2006-10-05

申请号：US11097590

申请日：2005-04-01

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

公开(公告)号：US06396168B2

公开(公告)日：2002-05-28

申请号：US09782173

申请日：2001-02-12

申请人： Stefano Ghezzi ,  Donato Ferrario ,  Emilio Yero ,  Giovanni Campardo

发明人： Stefano Ghezzi ,  Donato Ferrario ,  Emilio Yero ,  Giovanni Campardo

IPC分类号： H03K19096

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

摘要： A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

摘要翻译： 可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。 属于同一列的晶体管可以彼此串联连接。 串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。 阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。 除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。 除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。

公开(公告)号：US5675539A

公开(公告)日：1997-10-07

申请号：US575953

申请日：1995-12-21

申请人： Jean-Michel Mirabel ,  Emilio Yero

发明人： Jean-Michel Mirabel ,  Emilio Yero

IPC分类号： G11C29/50 ,  G11C11/34

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： An integrated circuit memory that contains a device for the precharging and reading of the bit lines, including a precharging element, a current-voltage converter and a read circuit, further contains a test circuit to isolate the output of the converter from the precharging element and from the read circuit, to apply a test voltage to a cell of the memory through the converter and to measure the current in the cell.

摘要翻译： 包含用于对位线进行预充电和读取的装置的集成电路存储器，包括预充电元件，电流 - 电压转换器和读取电路，还包括用于将转换器的输出与预充电元件隔离的测试电路，以及 从读取电路，通过转换器将测试电压施加到存储器的单元，并测量单元中的电流。

公开(公告)号：US5406141A

公开(公告)日：1995-04-11

申请号：US88544

申请日：1993-07-06

申请人： Emilio Yero ,  Olivier Rouy

发明人： Emilio Yero ,  Olivier Rouy

IPC分类号： H03K17/687 ,  H03F1/52 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0175 ,  H03K3/01

CPC分类号： H03K17/102 ,  H03K3/356113

摘要： A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.

摘要翻译： 包括两个臂的高压开关电路，其中每个臂具有串联连接在高电压和地之间的P沟道负载晶体管，正向偏置二极管和N沟道开关晶体管。 N沟道晶体管的栅极由一个臂中的开关信号C和另一个臂中的互补开关信号C控制。 这样的结构使得负载发生的应力和开关电路的开关晶体管可以减小几个数量级。

公开(公告)号：US5303189A

公开(公告)日：1994-04-12

申请号：US663410

申请日：1991-03-01

申请人： Jean Devin ,  Emilio Yero ,  Claude Costabello

发明人： Jean Devin ,  Emilio Yero ,  Claude Costabello

IPC分类号： G11C7/12 ,  G11C16/24 ,  G11C16/26 ,  G11C11/34

CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C7/12

摘要： An erasable and electrically programmable memory with only few cells works at high speed in reading mode and is reliable. This is achieved by using a voltage limiter that limits the variation in the drain voltage of the memory cells.

摘要翻译： 一个可擦除和电可编程的存储器，只有少量单元在读取模式下以高速工作，并且可靠。 这通过使用限制存储器单元的漏极电压的变化的限压器来实现。