利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

216 条记录 (耗时 0.03 秒)

    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
    21.
    发明申请
    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
    集成电路供电结构

    公开(公告)号：US20090024972A1

    公开(公告)日：2009-01-22

    申请号：US12163025

    申请日：2008-06-27

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

    摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

    摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
    22.
    发明申请
    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS 有权
    优化低功率环境下计算效率的结构与方法

    公开(公告)号：US20090024859A1

    公开(公告)日：2009-01-22

    申请号：US11870575

    申请日：2007-10-11

    申请人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    发明人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    IPC分类号： G06F1/32

    CPC分类号： G06F1/26

    摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

    摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

    DYNAMIC OBJECT-LEVEL CODE TRANSLATION FOR IMPROVED PERFORMANCE OF A COMPUTER PROCESSOR
    24.
    发明申请
    DYNAMIC OBJECT-LEVEL CODE TRANSLATION FOR IMPROVED PERFORMANCE OF A COMPUTER PROCESSOR 失效
    用于改进计算机处理器性能的动态对象级代码转换

    公开(公告)号：US20080320286A1

    公开(公告)日：2008-12-25

    申请号：US12197613

    申请日：2008-08-25

    申请人： John E. Campbell ,  William T. Devine ,  Sebastian T. Ventrone

    发明人： John E. Campbell ,  William T. Devine ,  Sebastian T. Ventrone

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30174 ,  G06F9/3017

    摘要： A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.

    摘要翻译： 一种用于提高计算机处理器中的对象级指令流的效率的系统和方法。 用于在RISC架构的计算机处理器中从对象级指令流生成翻译指令的翻译逻辑和执行翻译指令的执行单元集成到处理器中。 翻译逻辑将多个对象级指令的功能组合成单个转换的指令，该指令与非翻译指令相比可以被分派到单个执行单元，否则将被顺序地分派到单独的执行单元。 因此，可以扩展处理器的吞吐量，因为每个周期可以调度的指令的数量被扩展。

    System and Method for Dynamically Executing a Function in a Programmable Logic Array
    25.
    发明申请
    System and Method for Dynamically Executing a Function in a Programmable Logic Array 失效
    用于在可编程逻辑阵列中动态执行功能的系统和方法

    公开(公告)号：US20080290896A1

    公开(公告)日：2008-11-27

    申请号：US12185467

    申请日：2008-08-04

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

    摘要： A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

    摘要翻译： 可重构逻辑阵列（RLA）系统，其包括RLA和用于在循环基础上重新编程RLA的编程器。 需要比RLA中包含的逻辑量​​大的函数（F）被划分为多个功能块。 程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
    26.
    发明申请
    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构

    公开(公告)号：US20080229265A1

    公开(公告)日：2008-09-18

    申请号：US12129748

    申请日：2008-05-30

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F17/5045

    摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。 特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

    System For Method Of Predicting Power Events In An Intermittent Power Environment And Dispatching Computational Operations Of An Integrated Circuit Accordingly
    27.
    发明申请
    System For Method Of Predicting Power Events In An Intermittent Power Environment And Dispatching Computational Operations Of An Integrated Circuit Accordingly 有权
    因此，在间歇电力环境中预测电力事件的方法系统和集成电路的调度运算

    公开(公告)号：US20080189567A1

    公开(公告)日：2008-08-07

    申请号：US11550573

    申请日：2006-10-18

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F11/07 ,  G06F11/30

    CPC分类号： C09K11/77 ,  G06F1/3203

    摘要： A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

    摘要翻译： 一种在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的系统和方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

    Programmable capacitors and methods of using the same
    29.
    发明授权
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US07358823B2

    公开(公告)日：2008-04-15

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

    Data processing in digital systems
    30.
    发明授权
    Data processing in digital systems 有权
    数字系统中的数据处理

    公开(公告)号：US07353486B2

    公开(公告)日：2008-04-01

    申请号：US11272884

    申请日：2005-11-14

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

    摘要翻译： 包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。 可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。 在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间 允许移动，并将步进的方向和距离存储在映射运动寄存器中。 然后，功能块根据存储在映射运动寄存器中的方向和距离移动。