摘要:
A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.
摘要:
A series of Zener diodes (25) and an electronic power switch, such as an IGBT (18), are connected across a power supply. A circuit including a resistor (20) in series on the electronic switch, a threshold device (36, 38) connected to the resistor and a ramp generator with multiplier (40, 42, 44, 46, FIG. 2) or a thermal sensor (50, 44, 46 FIG. 3) detect the energy level dissipated in the electronic power switch when a transient occurs when the level exceeds a present value, the circuit supplies an output signal to a monostable circuit (26, 28, 48) to drive the electronic power switch with low resistance conditions for a preset time starting from the occurrence of the output signal. Another threshold device, connected to a resistor (30, 32), preferably senses the instantaneous power dissipated in the electronic switch to control the monostable circuit when the instantaneous power is higher than a preset threshold.
摘要:
A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.
摘要:
The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.
摘要:
The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.
摘要:
The need of implementing a second local oscillator in addition to the drive oscillator, for timing the different phases of the starting process of a half-bridge or bridge stage driving an external load, such as a fluorescent lamp, is avoided by employing a timing counter to count the number of oscillations produced by the drive oscillator, and a digital-to-analog converter for controlling the frequency of oscillation of the drive oscillator.
摘要:
A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the "set" and "reset" inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the "set" terminal of the flip-flop has a lower resistance than that of the other resistor.
摘要:
A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (I.sub.BIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective loads for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.
摘要:
The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.