公开(公告)号：US09818641B1

公开(公告)日：2017-11-14

申请号：US15271497

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/11

Abstract: A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An array of mandrels, a beta trench and a gamma trench are patterned into the structure. First inner spacers are formed on sidewalls of the beta trench and second inner spacers are formed on sidewalls of the gamma trench. The first and second inner spacers form a portion of a pattern. The pattern is etched into the dielectric stack to form an array of mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in an X direction. The portion of the pattern formed by the first and second inner spacers forms a first pair of cuts in a mandrel line and a second pair of cuts in a non-mandrel line respectively. The cuts are self-aligned in the Y direction.

公开(公告)号：US09818623B2

公开(公告)日：2017-11-14

申请号：US15077480

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche ,  Byoung Youp Kim ,  Craig Michael Child, Jr.

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/32

CPC classification number: H01L21/32 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US09691626B1

公开(公告)日：2017-06-27

申请号：US15077384

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L23/528

Abstract: A method of forming a pattern includes providing a structure having an etch mask layer disposed over a pattern layer disposed over a dielectric layer. Disposing first and second trench plugs having different material compositions in the etch mask layer, the first and second trench plugs overlaying gamma and beta block mask portions respectively of the pattern layer. Forming an array of self-aligned spacers disposed on sidewalls of mandrels, the spacers and mandrels defining alternating beta and gamma regions extending normally to the dielectric layer, the gamma region and beta regions extending though portions of the first and second trench plug respectively. Selectively etching the structure to remove any portion of the first trench plug within the beta region and any portion of the second trench plug within the gamma region. Selectively etching the structure to form a pattern in the pattern layer including the block mask portions.