公开(公告)号：US10579774B2

公开(公告)日：2020-03-03

申请号：US16008176

申请日：2018-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng Lan Lau ,  Manjunatha Prabhu ,  Vikrant Kumar Chauhan ,  Shawn Walsh

IPC: G06F17/50

Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.

公开(公告)号：US20190384885A1

公开(公告)日：2019-12-19

申请号：US16008176

申请日：2018-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng Lan Lau ,  Manjunatha Prabhu ,  Vikrant Kumar Chauhan ,  Shawn Walsh

IPC: G06F17/50

Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.

公开(公告)号：US10236350B2

公开(公告)日：2019-03-19

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/768

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.