公开(公告)号：US09590028B2

公开(公告)日：2017-03-07

申请号：US14948587

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64

CPC classification number: H01L28/60 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.

Abstract translation: 公开了一种通过提供高电容，超低剖面电容器结构和所得到的器件的集成工艺在插入晶片上形成沟槽电容器的方法。 实施例包括在插入物晶片的正面上形成聚合物嵌段，图案化和蚀刻聚合物嵌段以形成一个或多个沟槽，以及在聚合物嵌段的上表面和一个或多个沟槽中形成电容器。

公开(公告)号：US09466659B2

公开(公告)日：2016-10-11

申请号：US14326659

申请日：2014-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England ,  Mahesh Anant Bhatkar ,  Wanbing Yi ,  Juan Boon Tan

IPC: H01L21/4763 ,  H01L49/02 ,  H01L21/033 ,  H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/78 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L21/0335 ,  H01L21/2885 ,  H01L21/31058 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed. In one embodiment, the conductive portion(s) and the other conductive portion(s) define, at least in part, a conductive coil(s) of the element.

Abstract translation: 提供了形成诸如多层电感器或变压器的电路元件的晶片级方法。 所述方法包括例如：在衬底上的至少一层中形成电路元件的至少一个导电部分; 提供至少部分地覆盖所述元件的导电部分并且覆盖所述元件的导电部分的未固化的聚合物 - 电介质材料; 部分固化聚合物 - 电介质材料以获得部分硬化的聚合物介电材料; 并将部分硬化的聚合物电介质材料抛光至导电部分。 抛光使部分硬化的聚合物 - 电介质材料平坦化并且暴露导电部分的上表面，以便于在导电部分上方形成与元件电连接的元件的至少一个其它导电部分。 抛光后，完成聚合物 - 电介质材料的固化。 在一个实施例中，导电部分和另一个导电部分至少部分地限定该元件的导电线圈。

公开(公告)号：US09257383B2

公开(公告)日：2016-02-09

申请号：US14155886

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England

IPC: H01L21/20 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.

Abstract translation: 公开了一种通过提供高电容，超低剖面电容器结构和所得到的器件的集成工艺在插入晶片上形成沟槽电容器的方法。 实施例包括在插入物晶片的正面上形成聚合物嵌段，图案化和蚀刻聚合物嵌段以形成一个或多个沟槽，以及在聚合物嵌段的上表面和一个或多个沟槽中形成电容器。