公开(公告)号：US20190019876A1

公开(公告)日：2019-01-17

申请号：US15647403

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/165

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

公开(公告)号：US20180096894A1

公开(公告)日：2018-04-05

申请号：US15282211

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Hans-Juergen Thees

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0883 ,  H01L29/786

Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

公开(公告)号：US20170365680A1

公开(公告)日：2017-12-21

申请号：US15185593

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/51 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6656 ,  H01L29/786

Abstract: A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multi-layer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.

公开(公告)号：US09847347B1

公开(公告)日：2017-12-19

申请号：US15344856

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nilesh Kenkare ,  Nigel Chan

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/1203 ,  H01L21/31144 ,  H01L21/84 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

公开(公告)号：US09608112B2

公开(公告)日：2017-03-28

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

公开(公告)号：US10707330B2

公开(公告)日：2020-07-07

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L21/285 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

公开(公告)号：US10559490B1

公开(公告)日：2020-02-11

申请号：US16107563

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Ming-Cheng Chang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

公开(公告)号：US10522555B2

公开(公告)日：2019-12-31

申请号：US15944885

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

IPC: H01L21/02 ,  H01L27/11 ,  H01L21/311

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

公开(公告)号：US20190312042A1

公开(公告)日：2019-10-10

申请号：US16416477

申请日：2019-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

IPC: H01L27/11

Abstract: A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration.

公开(公告)号：US10418380B2

公开(公告)日：2019-09-17

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/266

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.