公开(公告)号：US09793294B1

公开(公告)日：2017-10-17

申请号：US15455588

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684

Abstract: A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.

公开(公告)号：US09673210B1

公开(公告)日：2017-06-06

申请号：US15053365

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Joerg Schmid

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/823842 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/165 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66833 ,  H01L29/7848 ,  H01L29/792

Abstract: A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.

公开(公告)号：US09634017B1

公开(公告)日：2017-04-25

申请号：US14959382

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11 ,  H01L29/51 ,  H01L21/28 ,  H01L21/265 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/788 ,  H01L27/11526 ,  G11C14/00 ,  G11C16/24 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/11521 ,  G11C14/0063 ,  G11C16/24 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76224 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7883

Abstract: A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.