公开(公告)号：US09293556B2

公开(公告)日：2016-03-22

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。

公开(公告)号：US20160163821A1

公开(公告)日：2016-06-09

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。

公开(公告)号：US20160035856A1

公开(公告)日：2016-02-04

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。

公开(公告)号：US09673210B1

公开(公告)日：2017-06-06

申请号：US15053365

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Joerg Schmid

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/823842 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/165 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66833 ,  H01L29/7848 ,  H01L29/792

Abstract: A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.

公开(公告)号：US09536992B2

公开(公告)日：2017-01-03

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。