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63 条记录 (耗时 0.018 秒)

    FIN-TYPE FIELD-EFFECT TRANSISTORS OVER ONE OR MORE BURIED POLYCRYSTALLINE LAYERS
    22.
    发明申请
    FIN-TYPE FIELD-EFFECT TRANSISTORS OVER ONE OR MORE BURIED POLYCRYSTALLINE LAYERS 有权

    公开(公告)号：US20210043624A1

    公开(公告)日：2021-02-11

    申请号：US16534361

    申请日：2019-08-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L29/04

    摘要： Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

    Neuromorphic circuit structure and method to form same
    23.
    发明授权
    Neuromorphic circuit structure and method to form same 有权

    公开(公告)号：US10909443B2

    公开(公告)日：2021-02-02

    申请号：US16283887

    申请日：2019-02-25

    申请人： GLOBALFOUNDRIES INC.

    发明人： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

    IPC分类号： G06N3/04 ,  H01L27/24 ,  H01L45/00 ,  H01L29/872

    摘要： Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

    Structures and SRAM bit cells integrating complementary field-effect transistors
    25.
    发明授权
    Structures and SRAM bit cells integrating complementary field-effect transistors 有权

    公开(公告)号：US10818674B2

    公开(公告)日：2020-10-27

    申请号：US16295485

    申请日：2019-03-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

    摘要： Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

    Nanosheet field-effect transistor with substrate isolation
    26.
    发明授权
    Nanosheet field-effect transistor with substrate isolation 有权

    公开(公告)号：US10714567B2

    公开(公告)日：2020-07-14

    申请号：US16185881

    申请日：2018-11-09

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Julien Frougier ,  Ruilong Xie

    IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L29/78

    摘要： Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A sacrificial layer is epitaxially grown on a bulk semiconductor substrate, a plurality of epitaxial semiconductor layers are epitaxially grown over the sacrificial layer, and the sacrificial layer and the plurality of epitaxial semiconductor layers are patterned to form a fin. A first portion of the first sacrificial layer is removed to form a first cavity arranged between the plurality of epitaxial semiconductor layers and the bulk semiconductor substrate, and a first dielectric material is deposited in the first cavity. A second portion of the first sacrificial layer, which is located adjacent to the first dielectric material in the first cavity, is removed to form a second cavity between the first fin and the bulk semiconductor substrate. A second dielectric material is deposited in the second cavity.

    Airgap spacers formed in conjunction with a late gate cut
    27.
    发明授权
    Airgap spacers formed in conjunction with a late gate cut 有权

    公开(公告)号：US10679894B2

    公开(公告)日：2020-06-09

    申请号：US16185799

    申请日：2018-11-09

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

    IPC分类号： H01L21/768 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

    摘要： Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

    GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH AIR-GAP INNER SPACERS AND METHODS
    28.
    发明申请
    GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH AIR-GAP INNER SPACERS AND METHODS 审中-公开

    公开(公告)号：US20200083352A1

    公开(公告)日：2020-03-12

    申请号：US16123160

    申请日：2018-09-06

    申请人： GLOBALFOUNDRIES INC.

    发明人： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

    摘要： Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.

    NANOSHEET FIELD-EFFECT TRANSISTORS FORMED WITH SACRIFICIAL SPACERS
    29.
    发明申请
    NANOSHEET FIELD-EFFECT TRANSISTORS FORMED WITH SACRIFICIAL SPACERS 审中-公开

    公开(公告)号：US20200066894A1

    公开(公告)日：2020-02-27

    申请号：US16106291

    申请日：2018-08-21

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Julien Frougier ,  Ruilong Xie ,  Daniel Chanemougame

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

    摘要： Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.