公开(公告)号：US20190279708A1

公开(公告)日：2019-09-12

申请号：US16424605

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sreenivasula Reddy Dhani Reddy ,  Sreejith Chidambaran ,  Binu Jose ,  Venkatraghavan Bringivijayaraghavan

IPC: G11C11/412 ,  G11C11/408 ,  G11C11/419 ,  G11C7/12

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

公开(公告)号：US20190244658A1

公开(公告)日：2019-08-08

申请号：US15891619

申请日：2018-02-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sreenivasula Reddy Dhani Reddy ,  Sreejith Chidambaran ,  Binu Jose ,  Venkatraghavan Bringivijayaraghavan

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/408 ,  G11C7/12

CPC classification number: G11C11/412 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/419 ,  H03K19/1776

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

公开(公告)号：US10217507B2

公开(公告)日：2019-02-26

申请号：US15345544

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Sreejith Chidambaran ,  Igor Arsovski

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

公开(公告)号：US10199095B1

公开(公告)日：2019-02-05

申请号：US15693637

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Venkatraghavan Bringivijayaraghavan ,  Vinay Bhat Soori

IPC: G11C11/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.

公开(公告)号：US10170164B1

公开(公告)日：2019-01-01

申请号：US15895001

申请日：2018-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/00 ,  G11C7/06

Abstract: Embodiments of the present disclosure provide a circuit structure including: a circuit driven by first and second sense amplifier (SA) output; a first driver having a first PMOS coupled to a node and to a pair of serially coupled NMOSs, wherein the first SA output is coupled to the first PMOS and the first NMOS of the first driver; a second driver having a second PMOS coupled to a node and a pair of coupled NMOSs, wherein the second SA output is coupled to the second PMOS and second NMOS of the second driver; a first and second supply PMOS, wherein first supply PMOS is coupled to the node of the first driver and to the second supply PMOS and first NMOS of the second driver, and wherein the second supply PMOS is coupled to node of second driver and to the first supply PMOS and second NMOS of first driver.

公开(公告)号：US10020809B2

公开(公告)日：2018-07-10

申请号：US15269139

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: H03K19/018 ,  H03K19/0185 ,  H03K3/356 ,  G11C11/418

CPC classification number: H03K19/018507 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/417 ,  G11C11/418 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173 ,  H03K3/356191

Abstract: The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.

公开(公告)号：US20180130521A1

公开(公告)日：2018-05-10

申请号：US15345544

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Sreejith Chidambaran ,  Igor Arsovski

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

公开(公告)号：US09405468B2

公开(公告)日：2016-08-02

申请号：US14276025

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Saurabh Chadha ,  Abhijit Saurabh ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F3/00 ,  G06F3/06 ,  G11C5/14 ,  G11C5/06 ,  G06F11/16 ,  G06F11/07 ,  G06F11/30 ,  G06F13/40 ,  G06F13/16 ,  G06F13/28 ,  G06F11/20

CPC classification number: G06F3/06 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2017 ,  G06F11/2092 ,  G06F11/3027 ,  G06F11/3034 ,  G06F13/1684 ,  G06F13/287 ,  G06F13/4068 ,  G11C5/06 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Abstract translation: 用于存储器设备控制的系统可以包括堆叠的存储器设备和存储器控制器。 堆叠的存储器件可以包括通过电互连连接到封装衬底的芯片堆叠。 堆叠可以包括多个存储器芯片，主控制芯片和次级控制芯片。 主控制芯片和次控制芯片可以通过内部数据总线电连接到多个存储器芯片。 主控制芯片可以具有在内部数据总线和第一外部数据总线之间提供接口的逻辑。 辅助控制芯片可以具有在内部数据总线和第二外部数据总线之间提供接口的逻辑。

公开(公告)号：US09251890B1

公开(公告)日：2016-02-02

申请号：US14577113

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navin Agarwal ,  Igor Arsovski ,  Venkatraghavan Bringivijayaraghavan ,  Krishnan S. Rengarajan

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/10 ,  G11C7/04 ,  G11C11/4096 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/109 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/06 ,  G11C29/12015

Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Abstract translation: 具有年龄检测和校正（ADAC）电路的存储器件，其检测由偏置温度不稳定性疲劳引起的偏差（即，随时间累积的偏置温度不稳定性应力），并且通过选择性地调整比例（在时间上测量）来计数偏斜， 的活动状态操作到空闲状态操作。 另外，使用类似的ADAC电路的存储器老化装置。