公开(公告)号：US20200295187A1

公开(公告)日：2020-09-17

申请号：US16886193

申请日：2020-05-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20160276480A1

公开(公告)日：2016-09-22

申请号：US15169495

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US20160190253A1

公开(公告)日：2016-06-30

申请号：US14942566

申请日：2015-11-16

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160013206A1

公开(公告)日：2016-01-14

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract translation: 一种集成电路，包括：UTBOX层; 第一个电池，包括：FDSOI晶体管; 分离晶体管的第一STI; 位于一个晶体管下方并位于UTBOX层之下的第一接地平面; 第一口井 第二个电池，包括：FDSOI晶体管; 分离晶体管的第二STI; 位于一个晶体管下方并位于UTBOX层之下的第二接地平面; 第二口井 分离细胞的第三STI，到达第一和第二孔的底部; 连续地在第一和第二阱下方延伸的深阱，具有在第三STI下面的部分，其掺杂密度比第一和第二STI下面的深井的掺杂密度高至少50％。

公开(公告)号：US20160013205A1

公开(公告)日：2016-01-14

申请号：US14771025

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract translation: 一种集成电路，包括：第一单元，包括：FDSOI晶体管; 位于晶体管下方的UTBOX层; 第一阱位于绝缘体层之下并位于晶体管下方，第一阱具有第一类掺杂; 具有第二类型掺杂的第一接地平面，位于所述晶体管中的一个之下且在所述绝缘体层和所述第一阱之间; 分离晶体管并与绝缘体层交叉的第一STI; 第一导电元件，其形成位于第一STI之下的第一阱和第一接地平面之间的电连接; 包括第二井的第二池; 分离所述电池的第二STI，穿过所述绝缘体层并到达所述第一和第二阱的底部。

公开(公告)号：US20190252551A1

公开(公告)日：2019-08-15

申请号：US16355398

申请日：2019-03-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20180315850A1

公开(公告)日：2018-11-01

申请号：US16026663

申请日：2018-07-03

Applicant: STMicroelectronics, Inc.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20150097212A1

公开(公告)日：2015-04-09

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre MORIN ,  Qing LIU ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7842

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

Abstract translation: 一种用于形成半导体器件的方法包括在应力半导体绝缘体晶片的应力半导体层上形成掩模层。 形成包围应力半导体层的隔离沟槽。 隔离沟槽延伸穿过掩模层并穿过SOI晶片的氧化物层。 绝缘体形成在隔离沟槽中。 在电介质体和应力半导体层的相邻侧壁上形成松弛减小衬垫。 应力半导体层上的掩模层被去除。

公开(公告)号：US20200161299A1

公开(公告)日：2020-05-21

申请号：US16751036

申请日：2020-01-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  Prasanna KHARE ,  Nicolas LOUBET

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L21/84

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20180182902A1

公开(公告)日：2018-06-28

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01H49/00 ,  B82B3/00 ,  H01H1/00 ,  H01H59/00 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.