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    INTEGRATED CANTILEVER SWITCH
    2.
    发明申请
    INTEGRATED CANTILEVER SWITCH 审中-公开

    公开(公告)号：US20190393358A1

    公开(公告)日：2019-12-26

    申请号：US16564860

    申请日：2019-09-09

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306

    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

    REDUCED TRENCH PROFILE FOR A GATE
    6.
    发明申请
    REDUCED TRENCH PROFILE FOR A GATE 有权
    减少一个门口的情况

    公开(公告)号：US20160181384A1

    公开(公告)日：2016-06-23

    申请号：US14581741

    申请日：2014-12-23

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen YEH

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

    Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

    Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

    CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD
    7.
    发明申请
    CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD 审中-公开
    具有低电阻接触和制造方法的CMOS结构

    公开(公告)号：US20150243660A1

    公开(公告)日：2015-08-27

    申请号：US14189509

    申请日：2014-02-25

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

    IPC: H01L27/092 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238

    Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

    Abstract translation: 一种制造CMOS集成电路结构的方法和CMOS集成电路结构。 该方法包括产生一个或多个n型阱，产生一个或多个p型阱，产生嵌入在一个或多个n型阱中的每一个中的一个或多个pFET源极漏极，产生一个或多个nFET源极漏极 嵌入在所述一个或多个p型阱中的每一个中，产生覆盖所述一个或多个pFET源极漏极中的每一个的pFET触点，以及产生覆盖所述一个或多个nFET源极漏极中的每一个的nFET触点。 一个或多个pFET源极漏极中的每一个的材料包括掺杂有p型材料的硅; 一个或多个nFET源极漏极中的每一个的材料包括掺杂有n型材料的硅; 每个pFET触点的材料包括硅化镍; 并且每个nFET接触的材料包括硅化钛。

    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS
    8.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS 有权
    使用TRENCH隔离区域制造半导体器件以维持通道应力的方法

    公开(公告)号：US20150099335A1

    公开(公告)日：2015-04-09

    申请号：US14048282

    申请日：2013-10-08

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing LIU ,  Nicolas LOUBET

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203

    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.

    Abstract translation: 用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括在绝缘体上硅（SOI）晶片的半导体层中形成横向相邻的第一和第二有源区。 应力诱导层形成在第一有源区上方以赋予应力。 沟槽隔离区形成为包围应力诱导层的第一有源区和相邻部分。 去除应力诱导层，离开沟槽隔离区域以保持赋予第一有源区域的应力。

    VERTICAL TUNNELING FINFET
    9.
    发明申请
    VERTICAL TUNNELING FINFET 审中-公开

    公开(公告)号：US20200295187A1

    公开(公告)日：2020-09-17

    申请号：US16886193

    申请日：2020-05-28

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092

    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

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