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21.发明授权公开(公告)号：US08436677B2
公开(公告)日：2013-05-07
申请号：US12966624
申请日：2010-12-13
申请人： Lukas Kull , Martin L. Schmatz
发明人： Lukas Kull , Martin L. Schmatz
CPC分类号： G11C5/147 , H03M1/0863 , H03M1/12
摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.
摘要翻译： 为参考电压发生器提供了一种设计结构。 该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。 第一个电容为模数转换器提供电压参考。 控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。
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22.发明授权公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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公开(公告)号：US20090060091A1
公开(公告)日：2009-03-05
申请号：US11848599
申请日：2007-08-31
IPC分类号： H04L27/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。
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24.发明申请公开(公告)号：US20080218229A1
公开(公告)日：2008-09-11
申请号：US12100485
申请日：2008-04-10
IPC分类号： H03L7/06
CPC分类号： H03L7/02
摘要： Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.
摘要翻译： 具有锁相环电路的收发器系统中的电路块的抖动方法和控制电路，该锁相环电路包括振荡器，连接到所述振荡器的电荷泵以向所述振荡器加上或从所述振荡器加减电荷，以及连接到所述振荡器的低通滤波器 提供电荷泵。 电路连接到振荡器的输出端和电荷泵的输入端，以控制从电荷泵加到或减去的电荷量，以控制振荡器的带宽输出，从而减少锁相电路中的抖动。
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25.发明申请Clock and Data Recovery System and Method for Clock and Data Recovery Based on a Forward Error Correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US20080209296A1
公开(公告)日：2008-08-28
申请号：US12116151
申请日：2008-05-06
IPC分类号： G06F11/14
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.
摘要翻译： 基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟触发的接收数据的数据锁存器。 该系统还包括一个错误确定单元，用于确定哪个采样的接收数据是错误的，并且用于产生一个相位/频率校正信号。 此外，该系统包括用于根据校正信号产生采样时钟的时钟发生器。
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公开(公告)号：US20080007345A1
公开(公告)日：2008-01-10
申请号：US11425752
申请日：2006-06-22
IPC分类号： H03L7/00
CPC分类号： H03L7/02
摘要： Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.
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27.发明授权Error correcting code protected quasi-static bit communication on a high-speed bus 失效在高速总线上纠错代码保护的准静态位通信公开(公告)号：US08234540B2
公开(公告)日：2012-07-31
申请号：US12165788
申请日：2008-07-01
IPC分类号： H03M13/00
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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28.发明申请DESIGN STRUCTURE FOR A REFERENCE VOLTAGE GENERATOR FOR ANALOG TO DIGITAL CONVERTERS 失效用于模拟数字转换器的参考电压发生器的设计结构公开(公告)号：US20120146712A1
公开(公告)日：2012-06-14
申请号：US12966624
申请日：2010-12-13
申请人： Lukas Kull , Martin L. Schmatz
发明人： Lukas Kull , Martin L. Schmatz
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , H03M1/0863 , H03M1/12
摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.
摘要翻译： 为参考电压发生器提供了一种设计结构。 该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。 第一个电容为模数转换器提供电压参考。 控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。
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公开(公告)号：US07885365B2
公开(公告)日：2011-02-08
申请号：US11848599
申请日：2007-08-31
IPC分类号： H04L7/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。
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30.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
IPC分类号： H03M13/09
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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