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21.发明授权公开(公告)号：US07908493B2
公开(公告)日：2011-03-15
申请号：US11758798
申请日：2007-06-06
申请人： Andreas Bieswanger , Michael S. Floyd , Soraya Ghiasi , Steven P. Hartman , Thomas W. Keller, Jr. , Hye-Young McCreary , Karthick Rajamani , Freeman L. Rawson, III , Juan C. Rubio , Malcolm S. Ware
发明人： Andreas Bieswanger , Michael S. Floyd , Soraya Ghiasi , Steven P. Hartman , Thomas W. Keller, Jr. , Hye-Young McCreary , Karthick Rajamani , Freeman L. Rawson, III , Juan C. Rubio , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3203
摘要： A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.
摘要翻译： 提供了一种统一管理计算机系统的功率，性能和热量的机制。 该机制包含了以综合方式有效地解决管理计算系统的所有方面的元素，而不是独立的。 该机制采用基础设施进行实时测量反馈，用于调节系统活动的基础设施，组件操作级别和环境控制，用于保证响应/抢先动作的专用控制结构以及交互和集成组件。 该机制为用户级交互提供接口。 该机制还采用了多个时间尺度来解决功率/热问题的方法。 此外，该机制采用综合方法提高效率，而不是以单独的方式处理单个问题，而不是将功率/热问题的不同方面进行处理。
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公开(公告)号：US20100268930A1
公开(公告)日：2010-10-21
申请号：US12749179
申请日：2010-03-29
CPC分类号： G06F1/3203 , G06F11/3062 , G06F11/3096 , Y02D10/126
摘要： The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.
摘要翻译： 这些实施例提供了第一组计数器的分配的计数器，并且存储形成一组存储值的一组活动的活动的值。 该值包括计数乘以活动特有的权重因子。 功率管理器管理第一组计数器，接收一组要监视单元的活动，基于每个活动的发生频率和每个活动的功耗中的至少一个将该部分分组成子集，将所存储的 对应于每个子集中的每个活动的值以达到每个子集的总值，将每个子集的总值乘以与该子集对应的因子，以形成每个子集的缩放值，并且将每个子集的缩放值相加以形成 电力使用价值。
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23.发明授权Weighted event counting system and method for processor performance measurements 失效加权事件计数系统和处理器性能测量方法公开(公告)号：US07340378B1
公开(公告)日：2008-03-04
申请号：US11565106
申请日：2006-11-30
申请人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller, Jr. , Karthick Rajamani , Freeman Leigh Rawson, III , Juan C. Rubio
发明人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller, Jr. , Karthick Rajamani , Freeman Leigh Rawson, III , Juan C. Rubio
IPC分类号： G06F19/00
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
摘要翻译： 用于处理器性能测量的加权事件计数系统和方法提供低延迟和低误差性能测量能力。 加权性能计数器根据从处理器中的功能单元提供的多个事件信号累加性能计数。 根据具有处理器性能的每个事件之间的相关性，将不同的权重应用于事件信号。 权重可以由可编程寄存器提供，从而可以在程序控制下调整权重。 事件信号可以被组合以减少事件信号集合的位宽，其中在组合结果的单个字段中合并相互排斥的事件和具有根据子总计合并的相同权重的事件。 权重应用于组合结果，用于更新性能计数。 电源管理软件或硬件可以使用性能计数来对处理器的运行参数进行调整。
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24.发明授权公开(公告)号：US09164563B2
公开(公告)日：2015-10-20
申请号：US13479797
申请日：2012-05-24
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译： 提供了一种处理器电源噪声抑制方法。 在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。 该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。 一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。
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公开(公告)号：US08650431B2
公开(公告)日：2014-02-11
申请号：US12862492
申请日：2010-08-24
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.
摘要翻译： 一种用于在不中断在数据处理系统上执行的处理的情况下改变数据处理系统中的硬件的方法，系统和计算机程序产品。 可能需要对数据处理系统中的所选部分硬件进行硬件更改，例如修复硬件错误或实现系统更新。 响应于要求硬件对硬件的所选部分的改变的确定，所选择的部分执行的处理从硬件的所选部分移动到硬件的替代部分。 硬件更改应用于硬件的选定部分。 在应用硬件更改之后，硬件的所选部分返回供数据处理系统使用。
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公开(公告)号：US08635483B2
公开(公告)日：2014-01-21
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的条件集合，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与组件相关联的一组操作参数 被调整。
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27.发明申请SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH COMPARATOR INPUT TOGGLING 失效具有比较器输入功能的数字转换器的连续逼近模拟公开(公告)号：US20130088374A1
公开(公告)日：2013-04-11
申请号：US13270983
申请日：2011-10-11
IPC分类号： H03M1/38
CPC分类号： H03M1/0663 , H03M1/46
摘要： A successive approximation analog-to-digital converter (SA-ADC) includes a reference generator configured to output a first voltage and a second voltage; a comparator, the comparator having a positive input and a negative input thereto, the comparator being configured to receive the first voltage and the second voltage; and a comparator input toggle located between the reference generator and the comparator, wherein the comparator input toggle is configured to receive the first and second voltages from the reference generator and provide the first and second voltages to the comparator, wherein the comparator input toggle is further configured to switch between a first position, in which the first voltage is connected to the positive input, and the second voltage is connected to the negative input, and a second position, in which the second voltage is connected to the positive input, and the first voltage is connected to the negative input.
摘要翻译： 逐次逼近模数转换器（SA-ADC）包括被配置为输出第一电压和第二电压的参考发生器; 比较器，其具有正输入和负输入，所述比较器被配置为接收所述第一电压和所述第二电压; 以及位于所述参考发生器和所述比较器之间的比较器输入触发器，其中所述比较器输入触发器被配置为从所述参考发生器接收所述第一和第二电压并将所述第一和第二电压提供给所述比较器，其中所述比较器输入触发器进一步 被配置为在所述第一位置与所述正输入端连接所述第一电压并且所述第二电压连接到所述负输入端的第二位置和所述第二电压连接到所述正输入端的第二位置， 第一个电压连接到负输入。
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公开(公告)号：US08161493B2
公开(公告)日：2012-04-17
申请号：US12173771
申请日：2008-07-15
CPC分类号： G06F9/3851 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.
摘要翻译： 本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用 ，取决于核心的状态。 从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。 核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。
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29.发明授权公开(公告)号：US08032334B2
公开(公告)日：2011-10-04
申请号：US12342054
申请日：2008-12-22
申请人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
发明人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
CPC分类号： G06F11/30
摘要： A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.
摘要翻译： 用于识别要采样的传感器子集以减少传感器访问频率的系统。 系统确定系统中传感器的上升时间和记录值。 基于上升时间确定传感器的时间关键度。 该系统通过首先基于传感器上的一个或多个约束创建传感器子集来处理传感器。 系统监测传感器子集中的传感器的值，并且当传感器确定在传感器子集的下次调度采样之前，所述传感器子集中的传感器的值将超过阈值约束时，对传感器进行标记。 系统将标记的传感器移动到符合传感器约束的第二个传感器子集。
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30.发明申请DEVICE FOR AND METHOD OF WEIGHTED-REGION CYCLE ACCOUNTING FOR MULTI-THREADED PROCESSOR CORES 失效用于多线加工器的加权区域循环会计的装置和方法公开(公告)号：US20100287561A1
公开(公告)日：2010-11-11
申请号：US12173771
申请日：2008-07-15
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.
摘要翻译： 本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用 ，取决于核心的状态。 从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。 核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。
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