公开(公告)号：US07495282B2

公开(公告)日：2009-02-24

申请号：US11626778

申请日：2007-01-24

申请人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

发明人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

摘要翻译： 一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。 控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。 可以通过等离子体氮化形成固定电荷层。

公开(公告)号：US20080170438A1

公开(公告)日：2008-07-17

申请号：US11626778

申请日：2007-01-24

申请人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

发明人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

摘要翻译： 一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。 控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。 可以通过等离子体氮化形成固定电荷层。

公开(公告)号：US20110309426A1

公开(公告)日：2011-12-22

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US08492224B2

公开(公告)日：2013-07-23

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US20120127779A1

公开(公告)日：2012-05-24

申请号：US13363252

申请日：2012-01-31

申请人： Roy E. Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

发明人： Roy E. Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

IPC分类号： G11C11/00

CPC分类号： H01L45/146 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/33 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.

摘要翻译： 可重写电阻切换存储单元包括串联的第一和第二电容器。 第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。 第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。 第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。 在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。 在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

公开(公告)号：US08693233B2

公开(公告)日：2014-04-08

申请号：US13363252

申请日：2012-01-31

申请人： Roy E Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

发明人： Roy E Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

IPC分类号： G11C11/00

CPC分类号： H01L45/146 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/33 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.

摘要翻译： 可重写电阻切换存储单元包括串联的第一和第二电容器。 第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。 第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。 第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。 在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。 在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

公开(公告)号：US20120199898A1

公开(公告)日：2012-08-09

申请号：US13451009

申请日：2012-04-19

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L27/115

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US20110186799A1

公开(公告)日：2011-08-04

申请号：US13020054

申请日：2011-02-03

申请人： James Kai ,  Henry Chien ,  George Matamis

发明人： James Kai ,  Henry Chien ,  George Matamis

IPC分类号： H01L29/04 ,  H01L21/16 ,  H01L23/52 ,  B82Y99/00

CPC分类号： B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149

摘要： A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

摘要翻译： 非易失性存储单元包括第一电极，操舵元件，与转向元件串联定位的存储元件，多个离散的导电纳米特征，通过绝缘矩阵彼此分离，其中多个离散的纳米 - 特征位于与存储元件直接接触的位置，以及第二电极。 替代的非易失性存储单元包括第一电极，转向元件，与转向元件串联的存储元件，多个分立的绝缘纳米特征，其通过导电矩阵彼此分离，其中多个分立的绝缘 纳米特征位于与存储元件直接接触的位置，以及第二电极。

公开(公告)号：US20080074920A1

公开(公告)日：2008-03-27

申请号：US11534139

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US07615445B2

公开(公告)日：2009-11-10

申请号：US11534135

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。