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    Re-writable Resistance-Switching Memory With Balanced Series Stack
    1.
    发明申请
    Re-writable Resistance-Switching Memory With Balanced Series Stack 有权
    具有平衡串联堆叠的可重写电阻切换存储器

    公开(公告)号：US20120127779A1

    公开(公告)日：2012-05-24

    申请号：US13363252

    申请日：2012-01-31

    申请人： Roy E. Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

    发明人： Roy E. Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

    IPC分类号： G11C11/00

    CPC分类号： H01L45/146 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/33 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

    摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.

    摘要翻译： 可重写电阻切换存储单元包括串联的第一和第二电容器。 第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。 第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。 第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。 在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。 在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

    Triangle two dimensional complementary patterning of pillars
    3.
    发明授权
    Triangle two dimensional complementary patterning of pillars 有权
    支柱三角形二维互补图案化

    公开(公告)号：US07781269B2

    公开(公告)日：2010-08-24

    申请号：US12216109

    申请日：2008-06-30

    申请人： Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

    发明人： Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

    IPC分类号： H01L21/82

    CPC分类号： H01L27/101 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物， 用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。 一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。 每三个相邻的柱形成等边三角形，每个柱包括半导体器件。 多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

    MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME
    4.
    发明申请
    MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权
    具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法

    公开(公告)号：US20120091427A1

    公开(公告)日：2012-04-19

    申请号：US12904802

    申请日：2010-10-14

    申请人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

    发明人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

    IPC分类号： H01L45/00 ,  H01L21/02

    CPC分类号： H01L27/2481 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

    摘要翻译： 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。

    Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same
    5.
    发明授权
    Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
    具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法

    公开(公告)号：US08841648B2

    公开(公告)日：2014-09-23

    申请号：US12904802

    申请日：2010-10-14

    申请人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

    发明人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

    IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/56

    CPC分类号： H01L27/2481 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

    摘要翻译： 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。

    Triangle two dimensional complementary patterning of pillars
    6.
    发明申请
    Triangle two dimensional complementary patterning of pillars 有权
    支柱三角形二维互补图案化

    公开(公告)号：US20090321789A1

    公开(公告)日：2009-12-31

    申请号：US12216109

    申请日：2008-06-30

    申请人： Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

    发明人： Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

    IPC分类号： H01L21/822 ,  H01L27/10

    CPC分类号： H01L27/101 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物， 用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。 一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。 每三个相邻的柱形成等边三角形，每个柱包括半导体器件。 多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
    9.
    发明授权
    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
    用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化

    公开(公告)号：US08809128B2

    公开(公告)日：2014-08-19

    申请号：US12911900

    申请日：2010-10-26

    申请人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    发明人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC分类号： H01L21/82 ,  H01L27/24

    CPC分类号： G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

    摘要翻译： 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

    Optimization of critical dimensions and pitch of patterned features in and above a substrate
    10.
    发明授权
    Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
    优化衬底中和图案上的图案特征的临界尺寸和间距

    公开(公告)号：US08766332B2

    公开(公告)日：2014-07-01

    申请号：US13613956

    申请日：2012-09-13

    申请人： James M. Cleeves ,  Roy E. Scheuerlein

    发明人： James M. Cleeves ,  Roy E. Scheuerlein

    IPC分类号： H01L29/80

    CPC分类号： H01L27/105 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

    摘要翻译： 在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。 本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。 存储器阵列的一个级别包括例如平行轨道和扇出区域。 希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。 这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在 轨道，并且在不太关键的扇出区域更放松。