Vertical MIM capacitors and method of fabricating the same
    22.
    发明授权
    Vertical MIM capacitors and method of fabricating the same 有权
    垂直MIM电容器及其制造方法

    公开(公告)号:US07416953B2

    公开(公告)日:2008-08-26

    申请号:US11263419

    申请日:2005-10-31

    IPC分类号: H01L21/20

    摘要: A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, the insulation layer is patterned to form a trench in a predetermined area of an outer electrode around the sacrificial plug. A fenced insulation layer is formed around the sacrificial plug simultaneously. After the sacrificial plug is removed, a metal layer is filled in the predetermined area of the core and outer electrodes. A vertical MIM capacitor comprising the core electrode, the fenced insulation layer, and the outer electrode is finally formed. The invention also provides a vertical MIM capacitor.

    摘要翻译: 一种制造垂直MIM电容器的方法。 在基板上形成绝缘层。 将绝缘层图案化以在芯电极的预定区域中形成开口。 然后,填充开口以形成牺牲塞。 随后,将绝缘层图案化以在牺牲插塞周围的外部电极的预定区域中形成沟槽。 围绕牺牲塞同时形成围栏绝缘层。 在去除牺牲塞之后,在芯和外电极的预定区域中填充金属层。 最终形成包括芯电极,围栏绝缘层和外电极的垂直MIM电容器。 本发明还提供一种垂直MIM电容器。

    System and method of protecting files from unauthorized modification or deletion
    23.
    发明申请
    System and method of protecting files from unauthorized modification or deletion 失效
    保护文件免遭未经授权的修改或删除的系统和方法

    公开(公告)号:US20080120727A1

    公开(公告)日:2008-05-22

    申请号:US11821165

    申请日:2007-06-22

    IPC分类号: H04L9/32

    CPC分类号: G06F21/6218 G06F2221/2147

    摘要: According to one embodiment of the invention, a method comprises receiving a write request for a file. A temporary file associated with the file is created in response to the write request. A write-lock is applied to the temporary file, namely the file includes a setting that restricts write access to only a component that created or opens the temporary file. Thereafter, the temporary file is closed to disable the write-lock and to enable a component that initiated the write request to access the temporary file.

    摘要翻译: 根据本发明的一个实施例,一种方法包括接收对文件的写入请求。 与该文件相关联的临时文件是响应写请求而创建的。 对临时文件应用写锁定,即该文件包括限制仅对创建或打开临时文件的组件的写访问权限的设置。 此后,临时文件关闭以禁用写锁定,并使启动写请求的组件能够访问临时文件。

    High-Level Bridge From PCIE to Extended USB
    24.
    发明申请
    High-Level Bridge From PCIE to Extended USB 失效
    从PCIE到扩展USB的高级桥

    公开(公告)号:US20080065796A1

    公开(公告)日:2008-03-13

    申请号:US11926636

    申请日:2007-10-29

    IPC分类号: G06F13/42

    摘要: An extended Universal-Serial Bus (EUSB) bridge to a host computer can have Peripheral Components Interconnect Express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

    摘要翻译: 到主机的扩展通用串行总线(EUSB)桥可以在桥的一侧具有外围组件互连Express(PCIE)协议层,在桥的另一侧可以具有高级桥接转换器 模块连接上层。 可以通过将桥与I / O控制器集成来消除PCIE物理,数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥,而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。 然后,EUSB数据有效载荷被传递到EUSB事务层,EUSB数据链路层和EUSB物理层,其在EUSB总线的两个差分对上驱动和感测物理电信号。

    Recycling Partially-Stale Flash Blocks Using a Sliding Window for Multi-Level-Cell (MLC) Flash Memory
    26.
    发明申请
    Recycling Partially-Stale Flash Blocks Using a Sliding Window for Multi-Level-Cell (MLC) Flash Memory 失效
    使用滑动窗口回收部分陈旧的闪存块用于多级单元(MLC)闪存

    公开(公告)号:US20070268754A1

    公开(公告)日:2007-11-22

    申请号:US11674645

    申请日:2007-02-13

    IPC分类号: G11C16/04 G06F12/00

    摘要: A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

    摘要翻译: 闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。 滑动窗口向下滑过几个闪光块。 检查最旧的块是否有效的数据页面,有效的页面被复制到滑动窗口的末尾,以便第一个块只有过时的页面。 然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。 当数据写入页面时,页面的有效位从擦除的未写入状态更改为有效状态。 之后,当新的主机数据替换该数据时,旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

    High-Speed Controller for Phase-Change Memory Peripheral Device
    27.
    发明申请
    High-Speed Controller for Phase-Change Memory Peripheral Device 失效
    用于相变存储器外围设备的高速控制器

    公开(公告)号:US20070255891A1

    公开(公告)日:2007-11-01

    申请号:US11770642

    申请日:2007-06-28

    IPC分类号: G06F12/00

    摘要: Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.

    摘要翻译: 外围设备将数据存储在非易失性相变存储器(PCM)中。 PCM单元具有具有高电阻非晶态和低电阻晶体态的合金电阻。 外围设备可以是多媒体卡/安全数字(MMC / SD)卡。 PCM控制器访问PCM存储器设备。 响应于主机总线事务中的命令,激活在PCM控制器中的CPU上执行的各种例程。 PCM系统通过执行预读存储器操作,预写存储器写操作,较大页存储器写操作,更宽数据总线存储器写操作中的一个或多个来增加一个或多个相变存储器件的吞吐量 多通道同时多存储体交错存储器读或写操作,写高速缓存存储器写操作及其任意组合。

    Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory
    28.
    发明申请
    Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory 失效
    用于多位单元闪存的单元降级和参考电压调整

    公开(公告)号:US20070201274A1

    公开(公告)日:2007-08-30

    申请号:US11737336

    申请日:2007-04-19

    IPC分类号: G11C11/34

    摘要: A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

    摘要翻译: 闪存具有多级单元(MLC),每个单元可以存储多个位。 当发生错误时,单元块可以降级到较少的位/单元,或用于存储关键数据(如引导代码)。 来自单个MLC的位在多个页面之间进行分区,以使用错误校正码(ECC)来提高错误的可校正性。 响应于校准寄存器,由参考电压发生器产生较高的参考电压,校准寄存器可编程为改变上参考电压。 从较高参考电压产生一系列减小的参考值,并将其与位线电压进行比较。 比较结果由翻译逻辑翻译,生成读取数据和编程过程中和编程不足的信号。 降级的单元格使用相同的真值表,但生成较少的读取数据位。 通过使用相同的子状态来读取降级和全密度MLC单元,噪声余量被不对称地改善。

    Method for manufacturing embroidery decorated cards
    29.
    发明申请
    Method for manufacturing embroidery decorated cards 审中-公开
    刺绣装饰卡制作方法

    公开(公告)号:US20070089332A1

    公开(公告)日:2007-04-26

    申请号:US11251504

    申请日:2005-10-17

    申请人: Charles Lee

    发明人: Charles Lee

    IPC分类号: G09F1/00

    CPC分类号: G09F1/06 B42D15/045

    摘要: A method for manufacturing cards decorated with embroidered fabrics is provided. Various kinds of drawings are embroidered on a fabric with threads of different colors. Firstly, a paper is cut into a shape of a long rectangle which is divided into three equal sections and one of which, the first section, has a window at the center therefore and three trapezoidal wings are formed along the three edges thereof, to one end of the short side of the rectangle, opposite to the first section, is connected a distorted trapezoid along the bottom side of which one trapezoid wing is developed. The first sheet of card stock is folded into four portions. A part of the first portion of the card stock, the frame, is cut out of various shapes. The embroidered fabric is cut into a certain size and adhered to the rear side of the frame with hand. The front side of the paper frame is decorated with various kinds of paintings, pictures, phrases and emblems.

    摘要翻译: 提供了一种用绣花织物装饰的卡片制造方法。 各种图纸都绣在具有不同颜色的线的织物上。 首先将纸切成长方形的形状,将其分割为三个相等的部分,其中一个部分在其中心有一个窗口,三个梯形翼沿其三个边缘形成一个 在与第一部分相对的矩形的短边的端部沿着其一侧梯形翼展开的底侧连接变形的梯形。 第一张纸卡片折叠成四部分。 卡片坯料的第一部分的一部分,框架被切割成各种形状。 将绣花织物切成一定尺寸,用手粘在框架的后侧。 纸框的正面装饰有各种绘画,图片,短语和标志。