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29 条记录 (耗时 0.041 秒)

    Enhancing strained device performance by use of multi narrow section layout
    22.
    发明授权
    Enhancing strained device performance by use of multi narrow section layout 有权
    通过使用多窄截面布局来增强设备的应变性能

    公开(公告)号：US07482670B2

    公开(公告)日：2009-01-27

    申请号：US11440613

    申请日：2006-05-24

    申请人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    发明人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    IPC分类号： H01L29/00

    CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

    摘要： A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

    摘要翻译： 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。

    Notched gate configuration for high performance integrated circuits
    23.
    发明授权
    Notched gate configuration for high performance integrated circuits 有权
    高性能集成电路的缺口门配置

    公开(公告)号：US06503844B2

    公开(公告)日：2003-01-07

    申请号：US09875320

    申请日：2001-06-06

    申请人： Giuseppe Curello

    发明人： Giuseppe Curello

    IPC分类号： H01L21302

    CPC分类号： H01L29/6656 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31116 ,  H01L29/42376

    摘要： A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric substrate and depositing a gate oxide layer, a conductive film layer, and a metal silicide layer over the gate oxide layer to form a conductive stack. A patterned silicon nitride mask layer is deposited over the conductive stack and over-etched to form a small notch in the metal silicide layer at each side of the patterned silicon nitride mask layer. This over-etching causes indentions to form in the conductive stack to result in decreased gate overlap between the gate and a source and drain which are later formed.

    摘要翻译： 高性能集成电路的缺口门配置。 制造缺口栅极配置的方法包括形成电介质基片并在栅极氧化物层上沉积栅极氧化物层，导电膜层和金属硅化物层以形成导电叠层。 图案化的氮化硅掩模层沉积在导电叠层上并被过蚀刻以在图案化的氮化硅掩模层的每一侧的金属硅化物层中形成小凹口。 这种过蚀刻导致在导电叠层中形成凹陷以导致栅极与稍后形成的源极和漏极之间的栅极重叠减少。

    Enhancing strained device performance by use of multi narrow section layout
    25.
    发明申请
    Enhancing strained device performance by use of multi narrow section layout 有权
    通过使用多窄截面布局来增强设备的应变性能

    公开(公告)号：US20050221566A1

    公开(公告)日：2005-10-06

    申请号：US10815911

    申请日：2004-03-31

    申请人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    发明人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/80 ,  H01L21/336 ,  H01L31/112

    CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

    摘要： A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

    摘要翻译： 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。