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    Enhancing strained device performance by use of multi narrow section layout
    1.
    发明授权
    Enhancing strained device performance by use of multi narrow section layout 有权
    通过使用多窄截面布局来增强设备的应变性能

    公开(公告)号：US07482670B2

    公开(公告)日：2009-01-27

    申请号：US11440613

    申请日：2006-05-24

    申请人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    发明人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    IPC分类号： H01L29/00

    CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

    摘要： A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

    摘要翻译： 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。

    Penetrating implant for forming a semiconductor device
    4.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US07943468B2

    公开(公告)日：2011-05-17

    申请号：US12059455

    申请日：2008-03-31

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Notched gate configuration for high performance integrated circuits
    8.
    发明授权
    Notched gate configuration for high performance integrated circuits 有权
    高性能集成电路的缺口门配置

    公开(公告)号：US06503844B2

    公开(公告)日：2003-01-07

    申请号：US09875320

    申请日：2001-06-06

    申请人： Giuseppe Curello

    发明人： Giuseppe Curello

    IPC分类号： H01L21302

    CPC分类号： H01L29/6656 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31116 ,  H01L29/42376

    摘要： A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric substrate and depositing a gate oxide layer, a conductive film layer, and a metal silicide layer over the gate oxide layer to form a conductive stack. A patterned silicon nitride mask layer is deposited over the conductive stack and over-etched to form a small notch in the metal silicide layer at each side of the patterned silicon nitride mask layer. This over-etching causes indentions to form in the conductive stack to result in decreased gate overlap between the gate and a source and drain which are later formed.

    摘要翻译： 高性能集成电路的缺口门配置。 制造缺口栅极配置的方法包括形成电介质基片并在栅极氧化物层上沉积栅极氧化物层，导电膜层和金属硅化物层以形成导电叠层。 图案化的氮化硅掩模层沉积在导电叠层上并被过蚀刻以在图案化的氮化硅掩模层的每一侧的金属硅化物层中形成小凹口。 这种过蚀刻导致在导电叠层中形成凹陷以导致栅极与稍后形成的源极和漏极之间的栅极重叠减少。

    Penetrating implant for forming a semiconductor device
    9.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08426927B2

    公开(公告)日：2013-04-23

    申请号：US13107783

    申请日：2011-05-13

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance
    10.
    发明申请
    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance 审中-公开
    制造具有用于改变窄宽度器件性能的抗卤素的MOSFET晶体管的方法

    公开(公告)号：US20070145495A1

    公开(公告)日：2007-06-28

    申请号：US11319815

    申请日：2005-12-27

    申请人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    发明人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/823412

    摘要： A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

    摘要翻译： 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并且通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。