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21.发明授权Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权利用侧壁间隔物特征在集成电路中形成磁隧道结公开(公告)号：US07531367B2
公开(公告)日：2009-05-12
申请号：US11333997
申请日：2006-01-18
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。
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公开(公告)号：US20080239784A1
公开(公告)日：2008-10-02
申请号：US12136091
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。
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公开(公告)号：US20080164617A1
公开(公告)日：2008-07-10
申请号：US11619623
申请日：2007-01-04
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。
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24.发明授权Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices 有权无磁阵列保护工艺流程，用于在磁性随机存取存储器件中形成互连通孔公开(公告)号：US06784091B1
公开(公告)日：2004-08-31
申请号：US10250133
申请日：2003-06-05
IPC分类号： H01L2128
CPC分类号： H01L27/222 , B82Y10/00 , H01L21/76802 , H01L27/228
摘要： A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.
摘要翻译： 用于在磁随机存取存储器（MRAM）器件中形成互连结构的方法包括在较低金属化层级上定义磁隧道结（MTJ）堆叠的阵列。 封装介电层形成在MTJ叠层阵列和下金属化层上。 然后，在密封介电层中限定通孔，并且在封装介电层上方和通孔开口内沉积平面层间电介质（ILD）层。 然后在ILD层内，在MTJ堆叠阵列和通孔开口上形成开口。
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公开(公告)号：US06660568B1
公开(公告)日：2003-12-09
申请号：US10290412
申请日：2002-11-07
申请人： Michael C. Gaidis
发明人： Michael C. Gaidis
IPC分类号： H01L2182
CPC分类号： H01L21/76802 , H01L21/76838 , H01L27/222
摘要： MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic circuit by setting the standard vertical dimension of the BEOL at the value that is suitable for logic circuits. In the areas where MRAM cells are to be placed, the (N+1)th level is etched separately. A standard etch is applied in logic areas and a deeper etch is applied in MRAM areas, so that the interlevel distance in the logic areas is the standard amount and the interlevel distance is MRAM areas is a lesser amount that is appropriate to accommodate the vertical dimensions of the material layers that go into the MRAM cells.
摘要翻译： 将MRAM单元放置在集成电路的上部区域（BEOL）中，同时保持良好的MRAM性能所需的尺寸，并且还通过将BEOL的标准垂直尺寸设置为适合于 逻辑电路。 在要放置MRAM单元的区域中，分别蚀刻（N + 1）级。 在逻辑区域中应用标准蚀刻，并且在MRAM区域中应用更深的蚀刻，使得逻辑区域中的层间距离是标准量，并且层间距离是MRAM区域是适于容纳垂直尺寸的较小量 的进入MRAM单元的材料层。
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26.发明授权Magnetic random access memory with synthetic antiferromagnetic storage layers and non-pinned reference layers 有权具有合成反铁磁存储层和非固定参考层的磁性随机存取存储器公开(公告)号：US08852762B2
公开(公告)日：2014-10-07
申请号：US13562868
申请日：2012-07-31
CPC分类号： G11C11/161 , H01L43/08 , H01L43/12 , Y10T428/31953 , Y10T428/32 , Y10T428/325
摘要： A synthetic antiferromagnetic device includes a reference layer having a first and second ruthenium layer, a magnesium oxide spacer layer disposed on the reference layer, a cobalt iron boron layer disposed on the magnesium oxide spacer layer and a third ruthenium layer disposed on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0 angstroms to 18 angstroms.
摘要翻译： 合成反铁磁装置包括具有第一和第二钌层的参考层，设置在参考层上的氧化镁间隔层，设置在氧化镁间隔层上的钴铁硼层和设置在钴铁硼上的第三钌层 第三钌层的厚度为约0埃至18埃。
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27.发明授权公开(公告)号：US08741664B2
公开(公告)日：2014-06-03
申请号：US13555368
申请日：2012-07-23
IPC分类号： H01L21/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675 , H01F1/0072 , H01F10/3254 , H01F41/308
摘要： A method of fabricating a self-aligning magnetic tunnel junction the method includes patterning a lithographic strip on a second magnetic material deposited on a first magnetic material that is disposed on a substrate, forming a top magnetic strip by etching an exposed portion of the second magnetic material, patterning a nanowire and a magnetic reference layer island over the substrate and forming the nanowire and the magnetic reference layer island by etching an exposed portion of the first magnetic layer and an exposed portion of the top magnetic strip, wherein an interface between the magnetic nanowire and the magnetic reference layer island is an magnetic tunnel junction aligned with a width of the nanowire.
摘要翻译： 一种制造自对准磁性隧道结的方法，包括在沉积在第一磁性材料上的第二磁性材料上图案化平版印刷条，所述第一磁性材料设置在基板上，通过蚀刻第二磁性体的暴露部分形成顶部磁条 材料，在衬底上图案化纳米线和磁参考层岛，并通过蚀刻第一磁性层的暴露部分和顶部磁条的暴露部分形成纳米线和磁性参考层岛，其中磁性 纳米线和磁性参考层岛是与纳米线的宽度对准的磁性隧道结。
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28.发明申请MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES 有权磁性隧道连接自动对位在磁性域移位寄存器存储器件公开(公告)号：US20140004625A1
公开(公告)日：2014-01-02
申请号：US13555368
申请日：2012-07-23
IPC分类号： H01L21/8246 , B82Y40/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675 , H01F1/0072 , H01F10/3254 , H01F41/308
摘要： A method of fabricating a self-aligning magnetic tunnel junction the method includes patterning a lithographic strip on a second magnetic material deposited on a first magnetic material that is disposed on a substrate, forming a top magnetic strip by etching an exposed portion of the second magnetic material, patterning a nanowire and a magnetic reference layer island over the substrate and forming the nanowire and the magnetic reference layer island by etching an exposed portion of the first magnetic layer and an exposed portion of the top magnetic strip, wherein an interface between the magnetic nanowire and the magnetic reference layer island is an magnetic tunnel junction aligned with a width of the nanowire.
摘要翻译： 一种制造自对准磁性隧道结的方法，包括在沉积在第一磁性材料上的第二磁性材料上图案化平版印刷条，所述第一磁性材料设置在基板上，通过蚀刻第二磁性体的暴露部分形成顶部磁条 材料，在衬底上图案化纳米线和磁参考层岛，并通过蚀刻第一磁性层的暴露部分和顶部磁条的暴露部分形成纳米线和磁性参考层岛，其中磁性 纳米线和磁性参考层岛是与纳米线的宽度对准的磁性隧道结。
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29.发明申请公开(公告)号：US20140003117A1
公开(公告)日：2014-01-02
申请号：US13539544
申请日：2012-07-02
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C19/0841
摘要： A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.
摘要翻译： 磁畴壁移位寄存器存储器件包括纳米线，沿纳米线设置的多个钉扎位置和基本上平行于纳米线布置并被配置为支持电流的控制线。
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30.发明授权Spin-torque based memory device with read and write current paths modulated with a non-linear shunt resistor 有权基于旋转力矩的存储器件，具有用非线性分流电阻调制的读和写电流路径公开(公告)号：US08270208B2
公开(公告)日：2012-09-18
申请号：US12701867
申请日：2010-02-08
IPC分类号： G11C11/00
CPC分类号： H01L27/224 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/5607 , H01L27/24 , H01L43/08 , H01L45/04 , H01L45/145
摘要： A spin-torque based memory device includes a write portion including a fixed ferromagnetic spin-polarizing layer, a spin-transport layer having a spin accumulation region formed above the fixed ferromagnetic spin-polarizing layer. The memory device further includes a read portion in electrical contact with the spin-transport layer. The read portion includes a free layer magnet, a read non-magnetic layer, and a reference layer. The memory device further includes a metal contact region formed overlying the read portion and a nonlinear resistor formed between an upper surface of the spin transport layer and the metal contact region and modulating write and read current paths depending on an applied voltage, thereby creating different current paths for write and read processes.
摘要翻译： 基于自旋扭矩的存储器件包括：写入部分，其包括固定铁磁自旋极化层，具有形成在固定铁磁自旋偏振层上方的自旋存储区域的自旋传输层。 存储器件还包括与自旋传输层电接触的读取部分。 读取部分包括自由层磁体，读取非磁性层和参考层。 存储器件还包括覆盖读取部分的金属接触区域和形成在自旋传输层的上表面与金属接触区域之间的非线性电阻，并且根据所施加的电压调制写入和读取电流路径，从而产生不同的电流 写入和读取过程的路径。
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