公开(公告)号：US20190012222A1

公开(公告)日：2019-01-10

申请号：US15645105

申请日：2017-07-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock ,  Shawn Walker ,  Paolo Faraboschi

IPC: G06F11/07 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

Abstract: In some examples, a controller includes a counter to track errors associated with a group of memory access operations, and processing logic to detect an error associated with the group of memory access operations, determine whether the detected error causes an error state change of the group of memory access operations, and cause advancing of the counter responsive to determining that the detected error causes the error state change of the group of memory access operations.

公开(公告)号：US20180276029A1

公开(公告)日：2018-09-27

申请号：US15467560

申请日：2017-03-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Derek Alan Sherlock

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/466

Abstract: A method may include receiving a first transaction request. The method may further include transmitting a retry response to the transaction request, which includes a first epoch identifier associated with a current epoch. The method may further include receiving a second transaction request, which includes a second epoch identifier associated with a previous epoch. The second transaction request may be fulfilled using a transaction resource reserved for the previous epoch.

公开(公告)号：US20180123966A1

公开(公告)日：2018-05-03

申请号：US15335878

申请日：2016-10-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock

IPC: H04L12/875 ,  H04L12/935 ,  H04L12/733

CPC classification number: H04L47/564 ,  H04L45/20 ,  H04L49/3009

Abstract: A fabric back pressure timeout transmitting device may include an arbiter, a first queue to supply packets to the arbiter and a second queue to supply packets to the arbiter, a first timer tracking time since transmission of a packet from the first queue with at least one packet in the first queue and a second timer tracking time since transmission of a packet from the second queue with at least one packet in the second queue. The first queue is designated to receive those packets that have a first number of remaining to destination hops. The second queue is designated to receive those packets that have a second number of remaining destination hops different than the first number.

公开(公告)号：US09929899B2

公开(公告)日：2018-03-27

申请号：US14911350

申请日：2013-09-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Michael Kontz ,  Derek Alan Sherlock

IPC: H04L12/24 ,  H04L12/703 ,  H04L12/801 ,  H04L12/939

CPC classification number: H04L41/0663 ,  H04L45/28 ,  H04L47/11 ,  H04L47/12 ,  H04L47/29 ,  H04L49/557

Abstract: A blockage is detected at a first link based on a delay and/or stoppage of transmission of a data message along the first link between first and second nodes of a plurality of nodes of a fabric. A snapshot message is sent along at least a second link between the first and second nodes in response to the blockage being detected. The second node may capture a fabric state at the second node in response to receiving the snapshot message, before a corrective action occurs.

公开(公告)号：US20170206126A1

公开(公告)日：2017-07-20

申请号：US15324945

申请日：2014-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F11/07 ,  G06F12/1009 ,  G06F12/06

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0623 ,  G06F12/0692 ,  G06F12/1009 ,  G06F13/40 ,  G06F2212/65 ,  G06F2212/684 ,  G06F2212/7201

Abstract: A system includes a central processing unit (CPU) to process data. A first memory management unit (MMU) in the CPU generates an external request to a bus for data located external to the CPU. An external fault handler in the CPU processes a fault response received via the bus. The fault response is generated externally to the CPU and relates to a fault being detected with respect to the external request.

公开(公告)号：US20170153983A1

公开(公告)日：2017-06-01

申请号：US15323700

申请日：2014-10-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F12/1027 ,  G06F12/14 ,  G06F11/07 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/145 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.

公开(公告)号：US11775443B2

公开(公告)日：2023-10-03

申请号：US15323700

申请日：2014-10-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F12/1027 ,  G06F11/07 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1081

CPC classification number: G06F12/1027 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/145 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.

公开(公告)号：US20200278807A1

公开(公告)日：2020-09-03

申请号：US15929725

申请日：2020-05-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.

公开(公告)号：US10740233B2

公开(公告)日：2020-08-11

申请号：US15768557

申请日：2015-10-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F12/00 ,  G06F12/0804 ,  G06F12/126

Abstract: According to an example, cache operations may be managed by detecting that a cacheline in a cache is being dirtied, determining a current epoch number, in which the current epoch number is associated with a store operation and wherein the epoch number is incremented each time a thread of execution completes a flush-barrier checkpoint, and inserting an association of the cacheline to the current epoch number into a field of the cacheline that is being dirtied.

公开(公告)号：US10691348B2

公开(公告)日：2020-06-23

申请号：US16274189

申请日：2019-02-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Shawn Walker

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: A system comprises a processor, a memory fabric, and a fabric bridge coupled to the memory fabric and the processor. The fabric bridge may receive, from the processor a first eviction request comprising first eviction data, transmit, to the processor, a message indicating the fabric bridge has accepted the first eviction request, transmit a first write comprising the first eviction data to the fabric, receive, from the processor, a second eviction request comprising second eviction data, and transmit a second write comprising the second eviction data to the fabric. Responsive to transmitting the second write request, the fabric bridge may transmit, to the processor, a message indicating the fabric bridge accepted the second eviction request, determine that the first write and the second write have persisted, and transmit, to the processor, a notification to the processor responsive to determining that the first write and the second write have persisted.