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公开(公告)号：US20180343210A1
公开(公告)日：2018-11-29
申请号：US15606402
申请日：2017-05-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Nicholas George McDonald , Gary Gostin , Darel N. Emmot , Gregg B. Lesartre , Al Davis , Derek Alan Sherlock
IPC: H04L12/935
Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.
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公开(公告)号：US20180077074A1
公开(公告)日：2018-03-15
申请号：US15263228
申请日：2016-09-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Derek Alan Sherlock , Gary Gostin
IPC: H04L12/823 , H04L12/24 , H04L12/863
CPC classification number: H04L47/32 , H04L41/0654 , H04L47/50
Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.
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公开(公告)号：US11126372B2
公开(公告)日：2021-09-21
申请号：US16680254
申请日：2019-11-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Russ W. Herrell , Gary Gostin , Gregg B Lesartre , Dale C. Morris
IPC: G06F3/06
Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.
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公开(公告)号：US11030061B2
公开(公告)日：2021-06-08
申请号：US16525086
申请日：2019-07-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gary Gostin , Erin A. Handgen
Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
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Patent Agency Ranking
公开(公告)号：US20200341898A1
公开(公告)日：2020-10-29
申请号：US16925870
申请日：2020-07-10
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Alexandros Daglis , Paolo Faraboschi , Qiong Cai , Gary Gostin
IPC: G06F12/0817 , G06F12/14 , G06F12/0831
Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.
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公开(公告)号：US10579519B2
公开(公告)日：2020-03-03
申请号：US15746618
申请日：2015-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Mark David Lillibridge , Gary Gostin , Paolo Faraboschi , Derek Alan Sherlock , Harvey Ray
Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
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公开(公告)号：US20190354447A1
公开(公告)日：2019-11-21
申请号：US16525086
申请日：2019-07-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gary Gostin , Erin A. Handgen
Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
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公开(公告)号：US20180203800A1
公开(公告)日：2018-07-19
申请号：US15746465
申请日：2015-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Alexandros Daglis , Paolo Fraboschi , Qiong Cai , Gary Gostin
IPC: G06F12/0817
CPC classification number: G06F12/0817 , G06F12/0811 , G06F12/0831 , G06F12/1441 , G06F12/1458 , G06F2212/1016 , G06F2212/1021 , G06F2212/502
Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.
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公开(公告)号：US20160232094A1
公开(公告)日：2016-08-11
申请号：US15099984
申请日：2016-04-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gary Gostin , Craig WARNER , John W. BOCKHAUS
CPC classification number: G06F12/0815 , G06F12/0223 , G06F12/06 , G06F12/0802 , G06F12/0873 , G06F12/10 , G06F13/16 , G06F2212/1024 , G06F2212/2024
Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.
Abstract translation: 提供了一种用于访问存储的计算机装置和相关方法。 在一个方面，控制器将存储器的数据块的地址范围映射到多个处理器中的至少一个处理器的可访问存储器地址范围。 在另一方面，控制器确保由多个处理器缓存在多个存储器中的数据块的副本是一致的。
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