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21.发明授权公开(公告)号：US06724511B2
公开(公告)日：2004-04-20
申请号：US10292661
申请日：2002-11-13
IPC分类号： G02F100
CPC分类号： G11C11/42 , G02F1/134336 , H01L27/156 , H01L27/307 , H01L27/3281 , H01L2251/5392
摘要： In a matrix-addressable optoelectronic apparatus which includes a functional medium in the form of an optoelectronically active material provided in a global layer in sandwich between a first and second electrode with parallel strip-like electrodes wherein the electrodes of the second electrode are oriented at an angle to the electrodes of the first electrode, functional elements are formed in the active material where respective electrodes overlap and correspond to optically active pixels in a display device or pixels in an optical detector, depending upon the active material used. In each of the first and second electrode, the electrodes are provided in a dense parallel configuration and mutually insulated by a thin film with a thickness that is only a fraction of the width of the electrodes.
摘要翻译： 在一种矩阵寻址光电子装置中，该光电子装置包括在具有平行条状电极的第一和第二电极之间夹层的全局层中设置为光电活性材料形式的功能介质，其中第二电极的电极定向为 取决于所使用的活性材料，在活性材料中形成功能元件，其中各个电极重叠并对应于显示装置中的光学有源像素或光学检测器中的像素。 在第一和第二电极中的每一个中，电极以致密的平行构造设置，并且通过薄膜相互绝缘，厚度仅为电极宽度的一部分。
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22.发明授权公开(公告)号：US06403396B1
公开(公告)日：2002-06-11
申请号：US09381995
申请日：1999-09-28
IPC分类号： H01L5140
CPC分类号： H01L51/0001 , H01L21/768 , H01L21/76888 , H01L21/76894 , H01L21/8221 , H01L51/0024 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： Electrically conducting and/or semiconducting structures are generated in three dimensions in a composite matrix including two or more materials provided in spatially separate and homogenous material structures. Materials undergo specific physical and/or chemical changes causing transition from electrically non-conducing to electrically conducting and semiconducting state. The material structures are radiated with a given intensity or frequency characteristic adapted to the specific response of the material. Spatially modulating the radiation according to a protocol representing a pattern of electrically conducing and semiconducting structures in the relevant material structures generates the two dimensional electrically conducting and semiconducting structures in the material structure. The composite matrix is provided with electrically conducting and semiconducting structures in three dimensions. Spectral ranges of the radiation include gamma, x-ray, ultraviolet, visible light, inferred, and microwave. Particle radiation used for irradiation includes elementary particles including protons, neutrons, electrons, ions, molecules, and material aggregates.
摘要翻译： 导电和/或半导体结构在三维生成复合基质中，包括在空间上分离和均匀的材料结构中提供的两种或多种材料。 材料经历特定的物理和/或化学变化，导致从电导通到导电和半导体状态的转变。 材料结构以适合材料的特定响应的给定强度或频率特性辐射。 根据表示相关材料结构中导电和半导体结构的图案的协议对辐射进行空间调制，在材料结构中产生二维导电和半导体结构。 复合矩阵在三维空间中提供导电和半导体结构。 辐射的光谱范围包括γ，X射线，紫外线，可见光，推测和微波。 用于照射的粒子辐射包括包括质子，中子，电子，离子，分子和材料聚集体的基本粒子。
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公开(公告)号：US6005791A
公开(公告)日：1999-12-21
申请号：US11522
申请日：1998-03-02
CPC分类号： G11C13/0014 , B82Y10/00 , G02F3/02 , G11C11/5664 , G11C13/00 , G11C13/0016 , G11C13/04 , G11C7/005
摘要： Addressable optical logic elements contain an optical memory substance, wherein, under the influence of an impressed magnetic, electromagnetic or electrical field or supplied energy, the memory substance can transfer from one physical or chemical state to a second physical or chemical state, wherein a physical or chemical state is assigned a specific logic value, and wherein a change in the logic element's physical or chemical state causes a change in the logic value and is implemented by the logic element being accessed and addressed magnetically, electromagnetically, electrically or optically for writing, reading, storing, erasing and switching of an assigned logic value.The optical logic device is especially usable for storing data or performing logic and arithmetic operations, wherein the device includes a plurality of optical logic elements, wherein the optical logic elements particularly are multistate, multistable optical logic elements, and even more particularly proximity-addressable optical logic elements, including an optical memory substance, wherein, under the influence of an impressed magnetic, electromagnetic or electrical field or supplied energy, the memory substance can transfer from one physical or chemical state to a second physical or chemical state, wherein a physical or chemical state is assigned a specific logic value, and wherein a change in the logic element's physical or chemical state causes a change in the logic value and is implemented by the logic element being accessed and addressed magnetically, electromagnetically, electrically or optically for writing, reading, storing, erasing and switching of an assigned logic value.
摘要翻译： PCT No.PCT / NO97 / 00154 Sec。 371日期1998年3月2日 102（e）1998年3月2日PCT 1997年6月12日PCT公布。 公开号WO97 / 48009 日期1997年12月18日适用的光学逻辑元件包含光学记忆物质，其中在受到外加的磁场，电磁场或电场或供应的能量的影响下，记忆物质可以从一个物理或化学状态转移到第二物理或化学 状态，其中物理或化学状态被分配特定逻辑值，并且其中所述逻辑元件的物理或化学状态的变化导致所述逻辑值的改变，并且被所述逻辑元件实现，并被磁性地，电磁地，电 或光学地用于写入，读取，存储，擦除和切换分配的逻辑值。 光学逻辑器件特别可用于存储数据或执行逻辑和算术运算，其中该器件包括多个光学逻辑元件，其中光学逻辑元件特别是多状态，多态光学逻辑元件，甚至更具体地是接近寻址光学 逻辑元件，包括光学记忆物质，其中在受到外加的磁场，电磁场或电场或所提供的能量的影响下，存储物质可以从一个物理或化学状态转移到第二物理或化学状态，其中物理或 化学状态被分配一个特定的逻辑值，并且其中逻辑元件的物理或化学状态的改变导致逻辑值的变化，并且被逻辑元件实现，被逻辑元件被磁性，电磁学，电学地或光学地用于写入，读取 ，存储，擦除和切换分配的逻辑值。
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24.发明授权公开(公告)号：US07248524B2
公开(公告)日：2007-07-24
申请号：US11168375
申请日：2005-06-29
IPC分类号： G11C7/04
CPC分类号： G11C29/021 , G11C11/22 , G11C29/02 , G11C29/028 , G11C2029/5002
摘要： In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.
摘要翻译： 在包括至少一个可矩阵寻址的铁电或驻极体存储装置的数据存储装置的加热和温度控制系统中，在存储装置中提供焦耳加热装置，温度确定装置与控制器电路连接，并且控制器电路被连接 具有外部电源，由前者的焦炭控制，焦耳加热意味着实现选定的工作温度。 在用于操作加热和温度控制系统的方法中，确定存储器件的环境温度或即时温度并将其与设定的标称最佳温度进行比较，并且在用于建立应用的控制参数的预定义算法中使用这些温度之间的差异 的焦耳加热装置的功率，以在其寻址操作期间实现存储装置中的选定的工作温度。
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25.发明授权Method for operating a passive matrix-addressable ferroelectric or electret memory device 失效用于操作无源矩阵寻址铁电或驻极体存储器件的方法公开(公告)号：US07215565B2
公开(公告)日：2007-05-08
申请号：US11027977
申请日：2005-01-04
申请人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
发明人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
IPC分类号： G11C11/22
摘要： In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.
摘要翻译： 在用于操作无源矩阵寻址铁电或驻极体存储器件的方法中，使用基于1/3电压选择规则的电压脉冲协议以便将干扰电压保持在最小值，所述电压脉冲协议包括用于读取和写入的周期 根据具有定义参数的电压脉冲的时间顺序进行擦除。 该方法包括刷新过程，其中选择用于刷新的单元和由存储器件控制器处理的刷新请求，关于正在进行或调度的存储器操作来监视和处理刷新请求，并且将具有所定义参数的刷新电压脉冲施加到存储器 选择用于刷新的单元，同时确保未选择的存储单元经受不影响这些单元的极化状态的零电压或电压。
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公开(公告)号：US07126176B2
公开(公告)日：2006-10-24
申请号：US10504860
申请日：2003-02-11
申请人： Hans Gude Gudesen , Per-Erik Nordal
发明人： Hans Gude Gudesen , Per-Erik Nordal
IPC分类号： H01L29/76
CPC分类号： H01L29/8615 , B82Y10/00 , G11C11/22 , H01L27/11502
摘要： In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more polymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer having a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.
摘要翻译： 在铁电或驻极体记忆体中，聚合物记忆材料是两种或更多种聚合物材料的混合物，所述聚合物材料与第一和第二电极接触。 每个电极是具有第一高导电层和导电聚合物层的复合多层，后者形成前者和记忆材料之间的接触。
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公开(公告)号：US06937499B2
公开(公告)日：2005-08-30
申请号：US10468888
申请日：2002-02-15
IPC分类号： G11C7/12 , G11C11/16 , G11C11/22 , G11C11/401
摘要： In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits (3; 4). An active word line (AWL) is selected by a multiplexer (7), while inactive word lines (IWL) are clamped to ground during readout. A second apparatus for performing the method is rather similar, but has only a single detection circuit (3, 4). An active word line (AWL) is selected by multiplexer (7) and a bit line (ABL) is selected by a multiplexer (9) provided between one end of the bit lines (BL) and the input of the detection circuit (3, 4), while inactive word and bit lines (IWL; IBL) are clamped to ground during readout.
摘要翻译： 在确定具有字和位线的无源矩阵可寻址数据存储设备中的存储器单元的逻辑状态的方法中，检测电流响应的分量并与探测电压相关联，并且将时间依赖电位施加到所选择的字 所述电位在幅度和时间上相互协调，使得在非活动字线和有源位线之间的交叉点上的所有或一些非寻址单元的结果电压仅被包含可忽略的电压 与探测电压暂时相关的分量。 根据本发明的用于执行该方法的第一装置通过检测电路（3; 4）提供有源字线（AWL）上的所有存储单元的顺序读出。 有源字线（AWL）由多路复用器（7）选择，而无效字线（IWL）在读出期间被钳位到地。 用于执行该方法的第二装置相当类似，但是仅具有单个检测电路（3,4）。 有源字线（AWL）由多路复用器（7）选择，位线（ABL）由设在位线（BL）的一端和检测电路（3）的输入端之间的多路复用器（9）选择， 4），而无效字和位线（IWL; IBL）在读出期间被钳位到地。
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公开(公告)号：US06894392B1
公开(公告)日：2005-05-17
申请号：US09463900
申请日：1999-06-02
IPC分类号： G06F1/16 , G11C17/00 , H01L21/768 , H01L21/822 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/10 , H01L51/40 , H01L23/48
CPC分类号： H01L21/02686 , G11C5/02 , G11C17/06 , H01L21/02532 , H01L21/02689 , H01L21/2026 , H01L21/768 , H01L21/76888 , H01L21/76894 , H01L21/8221 , H01L27/0688 , H01L27/1021 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/11 , H01L27/11502 , H01L51/0001 , H01L51/0024 , H01L2924/0002 , H01L2924/00
摘要： A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scaleable parallel architectures integrated with optimal interconnectivity in three dimensions.
摘要翻译： 可扩展集成数据处理装置，特别是微型计算机，包括具有一个或多个处理器的处理单元和具有一个或多个存储器的存储单元。 数据处理装置设置在载体基板（S）上并且包括相互叠放的彼此相邻的基本上平行的层（P，M，MP），处理单元和存储单元设置在一个或多个这样的层中，并且 以选定的组合形式具有选定数量的处理器和存储器的分离层。 在每个层中提供水平导电结构，其构成该层中的电内部连接，而且每个层包括提供与其它层的电连接以及数据处理装置的外部的电连接。 集成数据处理设备具有可扩展的架构，原则上可以配置几乎无限的处理器和存储器容量。 特别地，数据处理设备可以实现在三维中集成最佳互连性的各种形式的可扩展并行架构。
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公开(公告)号：US06804138B2
公开(公告)日：2004-10-12
申请号：US09899093
申请日：2001-07-06
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G09G3/20 , G09G3/3629 , G09G2300/06 , G09G2310/0251 , G09G2320/0209 , G11C7/06 , G11C7/1006 , G11C8/18
摘要： In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a “refresh/write cycle” during which the polarization of the cells connecting with selected word and bit lines are brought to correspond with a set of predetermined values.
摘要翻译： 在驱动无源矩阵显示器或存储阵列存储器阵列的方法中，该阵列包括具有磁滞的电可极化材料，特别是铁电材料，其中可以通过向字和位线施加电位或电压来切换各个单元的极化状态 在矩阵或阵列中，选择的字和位线上的电位被控制为接近或与n个预定义的电位电平中的一个一致，并且根据协议在时间上控制所有字和位线上的电位，使得字线依次 锁存到nWORD电位中选择的电位，而位线被顺序锁存到从nBIT电位中选择的电位，或者在连接到用于检测在位线或位线之间流动的电荷的电路的协议给定的定时序列的特定时段期间 和与其连接的单元。 该定时序列被提供有读取周期，在该循环期间检测在所选择的位线或连接到其之间的位线之间流动的电荷以及与所选择的字和位线连接的单元的极化被带到“刷新/写入周期” 对应于一组预定值。
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公开(公告)号：US06683803B2
公开(公告)日：2004-01-27
申请号：US10318137
申请日：2002-12-13
申请人： Hans Gude Gudesen , Per-Erik Nordal
发明人： Hans Gude Gudesen , Per-Erik Nordal
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： In a data storage apparatus comprising means for storing and retrieving data in respective write and read operations, and first and second set of addressing electrodes are provided, the latter set having electrodes that preferably are oriented orthogonally to the electrodes of the first set, and the electrodes (b, c) of the second set are provided as parallel twin electrodes located in parallel recesses or trenches (3) in the electrodes of the first set. The trenches compris a soft ferroelectric or electret memory material with piezoelectric properties such that memory cells (1) with two subcells (&agr;1, &agr;2) are formed in the trench (3) respectively between the electrodes (a) of the first set and the parallel twin electrodes (b, c) on either side of the latter. In a write operation data are encoded in the memory cells (1) by means of an applied voltage potential over the subcells (&agr;1, &agr;2). In a non-destructive readout operation of data encoded and stored in the memory cells (1) in this manner, the piezoelectric properties of the memory material (2) is employed for eliciting response signals from the subcells (&agr;1, &agr;2) of a memory cell (1) when the former are subjected to mechanical stresses in the lateral direction, such that the logical value stored in the memory cell (1) can be determined.
摘要翻译： 在一种数据存储装置中，包括用于在各自的写入和读取操作中存储和检索数据的装置，并且提供了第一和第二组寻址电极，后者组具有优选地与第一组电极正交定向的电极， 第二组的电极（b，c）设置为平行的双电极，位于第一组的电极中的平行的凹槽或沟槽（3）中。 沟槽包括具有压电特性的软铁电或驻极体记忆材料，使得分别在第一组的电极（a）和平行的电极（a）之间的沟槽（3）中形成具有两个子电池（α1，α2）的存储单元（1） 双电极（b，c）位于后两侧。 在写入操作中，通过在子单元（α1，α2）上施加的电压电位将数据编码在存储器单元（1）中。 在以这种方式编码和存储在存储器单元（1）中的数据的非破坏性读出操作中，存储材料（2）的压电特性用于从存储器的子单元（α1，α2）引出响应信号 当前者在横向受到机械应力时，使得可以确定存储在存储单元（1）中的逻辑值。
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