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    Communications system via data scrambling and associated methods
    21.
    发明授权
    Communications system via data scrambling and associated methods 有权
    通信系统通过数据加扰及相关方法

    公开(公告)号：US09473333B2

    公开(公告)日：2016-10-18

    申请号：US12028953

    申请日：2008-02-11

    申请人： Daniel M. Dreps ,  Frank D. Ferralolo ,  Robert J. Reese ,  Martin L. Schmatz

    发明人： Daniel M. Dreps ,  Frank D. Ferralolo ,  Robert J. Reese ,  Martin L. Schmatz

    IPC分类号： H04L9/00 ,  H04L25/03

    CPC分类号： H04L25/03866

    摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

    摘要翻译： 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

    Structure for a reference voltage generator for analog to digital converters
    22.
    发明授权
    Structure for a reference voltage generator for analog to digital converters 失效
    用于模数转换器的参考电压发生器的结构

    公开(公告)号：US08436677B2

    公开(公告)日：2013-05-07

    申请号：US12966624

    申请日：2010-12-13

    申请人： Lukas Kull ,  Martin L. Schmatz

    发明人： Lukas Kull ,  Martin L. Schmatz

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： G11C5/147 ,  H03M1/0863 ,  H03M1/12

    摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.

    摘要翻译： 为参考电压发生器提供了一种设计结构。 该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。 第一个电容为模数转换器提供电压参考。 控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。

    LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE
    24.
    发明申请
    LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE 有权
    低功率，低地区高速接收机架构

    公开(公告)号：US20090060091A1

    公开(公告)日：2009-03-05

    申请号：US11848599

    申请日：2007-08-31

    申请人： Christoph Hagleitner ,  Christian I. Menolfi ,  Martin L. Schmatz ,  Thomas H. Toifl

    发明人： Christoph Hagleitner ,  Christian I. Menolfi ,  Martin L. Schmatz ,  Thomas H. Toifl

    IPC分类号： H04L27/00

    CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/091 ,  H03L7/10 ,  H04L7/0008

    摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

    摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。

    ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY
    25.
    发明申请
    ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY 审中-公开
    使用反馈电路调整抖动控制的PLL带宽

    公开(公告)号：US20080218229A1

    公开(公告)日：2008-09-11

    申请号：US12100485

    申请日：2008-04-10

    申请人： Hayden C. Cranford ,  Ram Kelkar ,  Anjali R. Malladi ,  Martin L. Schmatz ,  Nina A. Shah

    发明人： Hayden C. Cranford ,  Ram Kelkar ,  Anjali R. Malladi ,  Martin L. Schmatz ,  Nina A. Shah

    IPC分类号： H03L7/06

    CPC分类号： H03L7/02

    摘要： Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.

    摘要翻译： 具有锁相环电路的收发器系统中的电路块的抖动方法和控制电路，该锁相环电路包括振荡器，连接到所述振荡器的电荷泵以向所述振荡器加上或从所述振荡器加减电荷，以及连接到所述振荡器的低通滤波器 提供电荷泵。 电路连接到振荡器的输出端和电荷泵的输入端，以控制从电荷泵加到或减去的电荷量，以控制振荡器的带宽输出，从而减少锁相电路中的抖动。

    Error correcting code protected quasi-static bit communication on a high-speed bus
    28.
    发明授权
    Error correcting code protected quasi-static bit communication on a high-speed bus 失效
    在高速总线上纠错代码保护的准静态位通信

    公开(公告)号：US08234540B2

    公开(公告)日：2012-07-31

    申请号：US12165788

    申请日：2008-07-01

    申请人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    发明人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    IPC分类号： H03M13/00

    CPC分类号： H03M13/13 ,  G06F11/10

    摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

    摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

    DESIGN STRUCTURE FOR A REFERENCE VOLTAGE GENERATOR FOR ANALOG TO DIGITAL CONVERTERS
    29.
    发明申请
    DESIGN STRUCTURE FOR A REFERENCE VOLTAGE GENERATOR FOR ANALOG TO DIGITAL CONVERTERS 失效
    用于模拟数字转换器的参考电压发生器的设计结构

    公开(公告)号：US20120146712A1

    公开(公告)日：2012-06-14

    申请号：US12966624

    申请日：2010-12-13

    申请人： Lukas Kull ,  Martin L. Schmatz

    发明人： Lukas Kull ,  Martin L. Schmatz

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  H03M1/0863 ,  H03M1/12

    摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.

    摘要翻译： 为参考电压发生器提供了一种设计结构。 该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。 第一个电容为模数转换器提供电压参考。 控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。

    Low-power, low-area high-speed receiver architecture
    30.
    发明授权
    Low-power, low-area high-speed receiver architecture 有权
    低功耗，低面积高速接收机架构

    公开(公告)号：US07885365B2

    公开(公告)日：2011-02-08

    申请号：US11848599

    申请日：2007-08-31

    申请人： Christoph Hagleitner ,  Christian I. Menolfi ,  Martin L. Schmatz ,  Thomas H. Toifl

    发明人： Christoph Hagleitner ,  Christian I. Menolfi ,  Martin L. Schmatz ,  Thomas H. Toifl

    IPC分类号： H04L7/00

    CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/091 ,  H03L7/10 ,  H04L7/0008

    摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

    摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。