公开(公告)号：US06738285B2

公开(公告)日：2004-05-18

申请号：US10190668

申请日：2002-07-09

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C1100

CPC分类号： G11C11/16

摘要： In a data read operation, a selected memory cell and a reference memory cell are connected to complementary first and second data lines via complementary first and second bit lines, respectively. A differential amplifier supplies passing currents of the memory cell and the reference cell to complementary first and second data buses, and amplifies a passing current difference between the first and second data buses occurring corresponding to an electric resistance difference between the memory cell and reference cell to produce a voltage difference of a polarity corresponding to the level of the stored data of the selected memory cell between first and second nodes.

摘要翻译： 在数据读取操作中，选择的存储单元和参考存储单元分别经由互补的第一和第二位线连接到互补的第一和第二数据线。 差分放大器将存储单元和参考单元的通过电流提供给互补的第一和第二数据总线，并且将与存储单元和参考单元之间的电阻差对应的第一和第二数据总线之间的通过电流差放大到 产生与第一和第二节点之间的所选存储单元的存储数据的电平相对应的极性的电压差。

公开(公告)号：US07233537B2

公开(公告)日：2007-06-19

申请号：US10260397

申请日：2002-10-01

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/2281

摘要： Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

摘要翻译： 正常存储单元和虚设单元连续地布置在存储器阵列中。 在数据读取操作中，第一和第二数据线分别连接到所选择的存储单元和虚拟单元，并且被提供有差分放大器的工作电流。 在第一和第二数据线的通过电流之间提供对应于从电压产生电路施加的第一和第二偏移控制电压之间的电压差的偏移，并且通过虚设单元的参考电流被设置为两种之间的水平 的电平对应于通过所选存储单元的数据读取电流的存储数据。

公开(公告)号：US20050024935A1

公开(公告)日：2005-02-03

申请号：US10932057

申请日：2004-09-02

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

摘要翻译： 在数据读取期间，根据行和列选择操作，激活感测使能信号以在形成包括数据线的当前路径和所选择的存储器单元之前开始数据线的充电。 早期完成数据线的充电，从而可以将开始数据读取所需的时间减少到数据线之间的通过电流差达到对应于所选存储单元的存储数据的电平的状态， 并且可以快速执行数据读取。

公开(公告)号：US5513142A

公开(公告)日：1996-04-30

申请号：US357007

申请日：1994-12-16

申请人： Kazutami Arimoto ,  Shigeki Tomishima ,  Hideto Hidaka

发明人： Kazutami Arimoto ,  Shigeki Tomishima ,  Hideto Hidaka

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/83 ,  G11C29/84

摘要： A memory array MA.sub.0 is divided into four sub memory arrays by sense amplifier strips. Word drivers belonging to each sub memory array are connected to a corresponding segment boosted signal line. A fuse is connected to each segment boosted signal line. By blowing out a fuse, the sub memory array corresponding to the blown out fuse is no longer used. The sub memory array that is no longer used is exchanged with a spare sub memory array of a spare memory array.

公开(公告)号：US5426615A

公开(公告)日：1995-06-20

申请号：US224461

申请日：1994-04-07

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C5/02

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines include lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of a power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器带平行并接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。

公开(公告)号：US5321646A

公开(公告)日：1994-06-14

申请号：US865142

申请日：1992-04-08

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4074 ,  G11C5/02 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C7/065

摘要： A power supply line is disposed parallel to a sense amplifier train including a plurality of sense amplifiers at the side of each subarray. The power supply line is connected to the sense amplifier included in the sense amplifier train via a plurality of drive transistors and a sense amplifier drive line.

摘要翻译： 电源线平行于包括在每个子阵列一侧的多个读出放大器的读出放大器串列布置。 电源线通过多个驱动晶体管和读出放大器驱动线路连接到包括在读出放大器列中的读出放大器。

公开(公告)号：US5602793A

公开(公告)日：1997-02-11

申请号：US417527

申请日：1995-04-06

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带，以及以网状形状布置的多个操作电源电位线和多个接地电位线。 操作电源电位线和接地电位线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到操作电源电位线和布置在感测放大器附近并与之并联的接地线。 驱动部件被设置用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 多个操作电源电位线和布置成网状的多个接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源电位和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的操作电源电位线和接地线，所以可靠且高速的感测操作是可能的，而与感测放大器驱动信号线的长度无关。

公开(公告)号：US5390140A

公开(公告)日：1995-02-14

申请号：US121853

申请日：1993-09-17

申请人： Shigeki Tomishima ,  Hideto Hidaka ,  Masakazu Hirose ,  Takahiro Tsuruda

发明人： Shigeki Tomishima ,  Hideto Hidaka ,  Masakazu Hirose ,  Takahiro Tsuruda

IPC分类号： H01L21/822 ,  G11C5/14 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  H01L21/82 ,  H01L27/04 ,  H03K17/16 ,  H03K19/0175 ,  G11C5/06

CPC分类号： G11C7/1057 ,  G11C5/14 ,  G11C7/1051 ,  H03K17/164

摘要： A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom. As a result, data is provided at a high speed and without overshoot, undershoot or ringing.

摘要翻译： 一种半导体集成电路器件，包括：接收电源电位的焊盘和接收两个形成在芯片上的接地电位的焊盘，以及连接到各个焊盘的电源电位线和接地电位线，沿着圆周形成环状 的芯片。 半导体集成电路器件包括为靠近预定电位焊盘的数据输出端子提供的第一数据输出电路和为远离预定电位焊盘的数据输出端提供的第二数据输出电路。 第一和第二数据输出电路根据内部输出数据信号以较低的速率和较高的速率以两个步骤将对应的数据输出端子驱动到预定电位。 第一和第二数据输出电路包括用于补偿和消除由于与预定焊盘的距离差而驱动对应的输出节点的部件。 因此，数据以高速提供，没有超调，下冲或振铃。

公开(公告)号：US5325336A

公开(公告)日：1994-06-28

申请号：US942320

申请日：1992-09-10

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines includes lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。

公开(公告)号：US5574397A

公开(公告)日：1996-11-12

申请号：US352021

申请日：1994-11-30

申请人： Shigeki Tomishima ,  Hideto Hidaka ,  Masakazu Hirose ,  Takahiro Tsuruda

发明人： Shigeki Tomishima ,  Hideto Hidaka ,  Masakazu Hirose ,  Takahiro Tsuruda

IPC分类号： H01L21/822 ,  G11C5/14 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  H01L21/82 ,  H01L27/04 ,  H03K17/16 ,  H03K19/0175 ,  H01J19/82

CPC分类号： G11C7/1057 ,  G11C5/14 ,  G11C7/1051 ,  H03K17/164

摘要： A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom. As a result, data is provided at a high speed and without overshoot, undershoot or ringing.