公开(公告)号：US06570801B2

公开(公告)日：2003-05-27

申请号：US09981517

申请日：2001-10-16

申请人： Munehiro Yoshida ,  Hiroshi Shinya

发明人： Munehiro Yoshida ,  Hiroshi Shinya

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.

公开(公告)号：US07385849B2

公开(公告)日：2008-06-10

申请号：US11512145

申请日：2006-08-30

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G11C11/34

CPC分类号： G11C29/20 ,  G06F11/1048 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/1201 ,  G11C29/36 ,  G11C29/42 ,  G11C2029/0407 ,  G11C2029/0411 ,  G11C2029/3602 ,  G11C2211/4062

摘要： A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M×N-bit data to the read/write buffer, and the read/write buffer outputs up to M×N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

摘要翻译： 公开了一种半导体集成电路器件。 该装置包括存储单元阵列，I / O缓冲器，读/写缓冲器，错误检查和校正电路以及初始化检查电路。 N位数据输入到I / O缓冲器，I / O缓冲器输出N位数据。 I / O缓冲器将N位数据输入到读/写缓冲器，读/写缓冲器将N位数据输出到I / O缓冲器。 存储单元阵列将高达MxN位数据输入到读/写缓冲器，读/写缓冲器向存储单元阵列输出高达MxN位的数据。 读/写缓冲器将可变数目的位写入存储单元阵列（N是等于或大于1的自然数，M是等于或大于2的自然数）。

公开(公告)号：US07223945B2

公开(公告)日：2007-05-29

申请号：US11352340

申请日：2006-02-13

申请人： Hiroshi Shinya ,  Takahiro Kitano

发明人： Hiroshi Shinya ,  Takahiro Kitano

IPC分类号： H05B1/02

CPC分类号： H01L21/67253 ,  H01L21/67098 ,  H01L21/67248

摘要： With respect to a substrate on which a resist solution is applied, the inplane uniformity of the quality of a resist film is improved in a heating processing carried out before exposure, and the yields of products are improved. A substrate on which a resist solution is applied is mounted on a heating plate in a processing vessel. Then, a purge gas is supplied into the processing vessel, and heating is started. Above the mounting position of the substrate, a thickness detecting sensor for monitoring the thickness of the resist film formed on the surface of the substrate is provided. When the thickness becomes a predetermined value or less, a control part cause a lift pin to upwardly move so as to increase the distance between the substrate and the heating plate. Thus, the heating value applied to the substrate decreases, and thereafter, only the solvent is volatilized without having a bad influence on a polymer in the resist film.

摘要翻译： 对于其上施加抗蚀剂溶液的基板，在曝光之前进行的加热处理中抗蚀剂膜的质量的面内均匀性得到改善，并且产品的收率得到改善。 将其上施加有抗蚀剂溶液的基板安装在处理容器中的加热板上。 然后，向处理容器供给净化气体，开始加热。 在基板的安装位置之上，设置有用于监测形成在基板的表面上的抗蚀剂膜的厚度的厚度检测传感器。 当厚度变为预定值或更小时，控制部分使升降销向上移动，以增加基板和加热板之间的距离。 因此，施加到基板的加热值降低，此后仅溶剂挥发而对抗蚀剂膜中的聚合物没有不利影响。

公开(公告)号：US07024798B2

公开(公告)日：2006-04-11

申请号：US11087690

申请日：2005-03-24

申请人： Tomohide Minami ,  Hiroshi Shinya ,  Takahiro Kitano

发明人： Tomohide Minami ,  Hiroshi Shinya ,  Takahiro Kitano

IPC分类号： F26B3/00

CPC分类号： H01L21/67109 ,  H01L21/67034 ,  Y10S134/902

摘要： A low-pressure dryer dries a substrate applied a coating solution thereon at low pressure. The dryer includes an airtight chamber installing a substrate table to place the substrate thereon; a diffuser plate, provided as facing the substrate placed on the substrate table with a gap, for discharging gas existing in the gap toward outside, the diffuser plate having a size almost the same as or larger than the substrate; a substrate-temperature adjuster, installed in the substrate table, for adjusting a temperature of the substrate; and a decompression mechanism for decompressing the airtight chamber. The diffuser plate has a temperature adjuster for making temperature adjustments to have a temperature difference between a first region and a second region of the diffuser plate, the first region facing a center region of the substrate, the second region being outside the first region and including a region facing an outer region of the substrate.

公开(公告)号：US20050005230A1

公开(公告)日：2005-01-06

申请号：US10878229

申请日：2004-06-29

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G06F11/10 ,  G06F7/02 ,  G06F11/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00 ,  H03M13/09

CPC分类号： G06F11/1008 ,  G06F2211/109 ,  G11C7/1006 ,  G11C7/1027 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096 ,  G11C2211/4062 ,  H03M13/09

摘要： A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

摘要翻译： 一种半导体集成电路装置，包括：存储单元阵列，错误检查和校正（ECC）电路，其在读取等待时间期间的数据读出时间执行从正常数据存储部分读出的读出数据的错误检查和校正操作，以及I / O缓冲区。 存储单元阵列包括正常数据存储部分和奇偶校验数据存储部分。 正常数据存储部分存储用于正常数据写入和正常数据读取的数据。 奇偶校验数据存储部存储用于错误检查和校正的奇偶校验数据。 在数据读取操作的读取延迟周期期间，EEC电路执行错误检查和校正从正常数据存储部分读出的读取数据。 在读取延迟周期过后，I / O缓冲器输出由ECC电路检查并校正的读取数据错误。

公开(公告)号：US06573031B2

公开(公告)日：2003-06-03

申请号：US10017450

申请日：2001-12-18

申请人： Hiroshi Shinya ,  Kazuyoshi Mizumoto ,  Kazuhisa Hayashida ,  Eiichi Sekimoto

发明人： Hiroshi Shinya ,  Kazuyoshi Mizumoto ,  Kazuhisa Hayashida ,  Eiichi Sekimoto

IPC分类号： G03F716

CPC分类号： H01L21/67253 ,  G03F7/168

摘要： A substrate coated with a coating solution is placed on a heating plate in a processing chamber in which an inert gas is circulating. The substrate is heated on the heating plate while the inert gas is circulating at an extremely small first circulating amount. The substrate is heated further on the heating plate while the inert gas is circulating at a second circulating amount larger than the first circulating amount. Detected is the density of the solvent in the processing chamber. The supply and exhaust amounts of the inert gas are controlled based on the density detected after the start of heating, so that an exhaust amount of the inert gas becomes a predetermined amount for a predetermined period until the solvent density reaches a predetermined density. A necessary control process is performed so that the solvent density reaches the predetermined density when the solvent density has not reached or exceeded the predetermined density after the predetermined period has elapsed. The two-time thermal-process or solvent-density control promotes evaporation of the resist solvent while restricting scattering of a photo-oxidizing agent included in the resist from being promoted beyond the wafer surface, thus achieving coated-film uniformity for the thermal process.

公开(公告)号：US5928390A

公开(公告)日：1999-07-27

申请号：US787862

申请日：1997-01-23

申请人： Hidetami Yaegashi ,  Takayuki Toshima ,  Masami Akimoto ,  Eiji Yamaguchi ,  Junichi Kitano ,  Takayuki Katano ,  Hiroshi Shinya ,  Naruaki Iida

发明人： Hidetami Yaegashi ,  Takayuki Toshima ,  Masami Akimoto ,  Eiji Yamaguchi ,  Junichi Kitano ,  Takayuki Katano ,  Hiroshi Shinya ,  Naruaki Iida

IPC分类号： H01L21/00 ,  H01L21/68 ,  B23P21/00 ,  B65G49/07 ,  H01L21/027

CPC分类号： H01L21/67178 ,  H01L21/67196 ,  H01L21/67225 ,  H01L21/67742 ,  Y10T29/41

摘要： A processing apparatus comprises a plurality of process unit groups each including a plurality of process units for subjecting an object to a series of processes, the process units being arranged vertically in multiple stages, an object transfer space being defined among the process unit groups, and a transfer mechanism for transferring the object, the transfer mechanism having a transfer member vertically movable in the object transfer space, the transfer member being capable of transferring the object to each of the process units. The processing apparatus further comprises a mechanism for forming a downward air flow in the object transfer space, a mechanism for controlling the quantity of the downward air flow, and a mechanism for controlling the pressure in the object transfer space. Thus, a variation in condition of the object transfer space is reduced.

摘要翻译： 处理装置包括多个处理单元组，每个处理单元组包括用于对象进行一系列处理的多个处理单元，处理单元以多级垂直排列，在处理单元组之间定义对象传送空间，以及 用于传送物体的传送机构，传送机构具有可在物体传送空间中垂直移动的传送部件，传送部件能够将物体传送到每个处理单元。 处理装置还包括用于在物体传送空间中形成向下的空气流的机构，用于控制向下的空气流量的机构，以及用于控制物体传送空间中的压力的​​机构。 因此，物体传送空间的状态的变化减小。

公开(公告)号：US5876280A

公开(公告)日：1999-03-02

申请号：US864937

申请日：1997-05-29

申请人： Junichi Kitano ,  Hiroshi Shinya ,  Takayuki Katano ,  Hidetami Yaegashi ,  Yasunori Kawakami ,  Fumihiko Kawano

发明人： Junichi Kitano ,  Hiroshi Shinya ,  Takayuki Katano ,  Hidetami Yaegashi ,  Yasunori Kawakami ,  Fumihiko Kawano

IPC分类号： G03F7/20 ,  H01L21/00 ,  H01L21/677 ,  F24F7/06

CPC分类号： H01L21/67173 ,  G03F7/7075 ,  H01L21/67017 ,  H01L21/67178 ,  H01L21/67778 ,  Y10S414/14

摘要： The present invention provides a substrate treating system for successively treating a plurality of substrates W under an air-conditioned environment. The system comprises an outer casing provided with a cassette transfer port through which a cassette is transferred, a cassette section having a cassette table arranged within an inner space surrounded by the outer casing for supporting the cassette transferred through the cassette transfer port, a sub-arm mechanism for taking the substrates one by one from the cassette section, a process section positioned adjacent to the cassette section and having a plurality of treating units for treating the substrates arranged therein, a main arm mechanism arranged within the process section for receiving the substrates from the sub-arm mechanism arranged in the cassette section and, then, transferring the received substrates to each of the treating units while transferring the treated substrates out of the treating units, an air supply mechanism for supplying a clean air to form a down-stream within the space surrounded by the outer casing, and a partition plate for partitioning the inner space surrounded by the outer casing not to interfere the down-flow of the air formed by the air supply mechanism, the partition plate having a substrate transfer port through which the substrate is transferred from one of the partitioned spaces to the other partitioned space.

摘要翻译： 本发明提供一种用于在空调环境下连续处理多个基板W的基板处理系统。 该系统包括设置有盒传送端口的外壳，盒传送通过该盒外壳，盒部具有设置在由外壳包围的内部空间内的盒式表台，用于支撑通过盒式磁带传送端口传送的磁带， 用于从盒部分逐个取出基板的臂机构，与盒部分相邻设置的处理部分，并具有用于处理布置在其中的基板的多个处理单元;布置在处理部分内用于接收基板的主臂机构 从设置在盒部中的副臂机构，然后将接收到的基板传送到每个处理单元，同时将处理过的基板从处理单元传送出去;空气供应机构，用于供应清洁空气， 在由外壳包围的空间内流动，以及用于分隔内部空间的分隔板 所述隔板由所述外壳围绕，不会干扰由所述供气机构形成的空气的向下流动，所述隔板具有基板传送口，所述基板通过所述基板传送口从所述分隔空间之一转移到所述另一个分隔空间。